01CDU6 datasheet(100/135 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F401xD STM32F401xE

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SPI interface characteristics

Unless otherwise specified, the parameters given in Table 61 for the SPI interface are

derived from tests performed under the ambient temperature, fPCLKx frequency and VDD

supply voltage conditions summarized in Table 14, with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 10

•

Capacitive load C = 30 pF

•

Measurement points are done at CMOS levels: 0.5VDD

Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate

function characteristics (NSS, SCK, MOSI, MISO for SPI).

Table 61. SPI dynamic characteristics(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fSCK

1/tc(SCK)

SPI clock frequency

Master mode, SPI1/4,

2.7 V < VDD < 3.6 V

MHz

Slave mode, SPI1/4,

2.7 V < VDD < 3.6 V

Slave transmitter/full-duplex mode,

SPI1/4, 2.7 V < VDD < 3.6 V

38(2)

Master mode, SPI1/2/3/4,

1.7 V < VDD < 3.6 V

Slave mode, SPI1/2/3/4,

1.7 V < VDD < 3.6 V

Duty(SCK)

Duty cycle of SPI clock

frequency

Slave mode

tw(SCKH)

tw(SCKL)

SCK high and low time Master mode, SPI presc = 2

TPCLK−1.5

TPCLK

TPCLK+1.5

tsu(NSS)

NSS setup time

Slave mode, SPI presc = 2

4TPCLK

th(NSS)

NSS hold time

Slave mode, SPI presc = 2

2TPCLK

tsu(MI)

Data input setup time

Master mode

tsu(SI)

Slave mode

2.5

th(MI)

Data input hold time

Master mode

th(SI)

Slave mode

2.5

ta(SO)

Data output access time Slave mode

tdis(SO)

Data output disable time Slave mode

tv(SO)

Data output valid time

Slave mode (after enable edge),

2.7 V < VDD < 3.6 V

-9.5

Slave mode (after enable edge),

1.7 V < VDD < 3.6 V

-9.5

th(SO)

Data output hold time

Slave mode (after enable edge),

2.7 V < VDD < 3.6 V

5.5

Slave mode (after enable edge),

1.7 V < VDD < 3.6 V

3.5

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