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TP3070 数据表(PDF) 13 Page - National Semiconductor (TI) |
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TP3070 数据表(HTML) 13 Page - National Semiconductor (TI) |
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13 / 26 page  Timing Specifications (Continued) Unless otherwise noted, limits printed in BOLD characters are guaranteed for V CC = +5V ±5%;VBB = −5V ±5%;TA = 0˚C to +70˚C (−40˚C to +85˚C for TP3070-X) by correlation with 100% electrical testing at T A = 25˚C. All other limits are assured by correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals specified at V CC = +5V, VBB = −5V, TA = 25˚C. All timing parameters are measured at V OH = 2.0V and VOL = 0.7V. See Definitions and Timing Conventions section for test methods information. Symbol Parameter Conditions Min Typ Max Units PCM INTERFACE TIMING t DBZ Delay Time, BCLK Low to D X0/1 D X0/1 Disabled is measured at VOL or V OH according to Figure 4 or Figure 5 Disabled if FS X Low, FSX Low to D X0/1 disabled if 8th BCLK 15 80 ns Low, or BCLK High to D X0/1 Disabled if FS X High −40˚C to +85˚C (TP3070-X) 15 100 ns t DBT Delay Time, BCLK High to TS X Low if FS X High, or FSX High to TS X Low if BCLK High (Non Delayed Mode); BCLK High to TS X Low (Delayed Data Mode) Load = 100 pF Plus 2 LSTTL Loads 60 ns t ZBT TRI-STATE Time, BCLK Low to TS X High if FSX Low, FSX Low to TS X High if 8th BCLK Low, or BCLK High to TS X High if FSX High 15 60 ns t DFD Delay Time, FS X/R Load = 100 pF Plus 2 LSTTL Loads, High to Data Valid Applies if FS X/R Rises Later than 80 ns BCLK Rising Edge in Non-Delayed Data Mode Only −40˚C to +85˚C (TP3070-X) 90 ns t SDB Setup Time, D R0/1 30 ns Valid to BCLK Low t HBD Hold Time, BCLK 15 ns Low to D R0/1 Invalid −40˚C to +85˚C (TP3070-X) 15 ns SERIAL CONTROL PORT TIMING f CCLK Frequency of CCLK 2048 kHz t WCH Period of CCLK High Measured from V IH to VIH 160 ns t WCL Period of CCLK Low Measured from V IL to VIL 160 ns t RC Rise Time of CCLK Measured from V IL to VIH 50 ns t FC Fall Time of CCLK Measured from V IH to VIL 50 ns t HCS Hold Time, CCLK Low CCLK1 10 ns to CS Low t HSC Hold Time, CCLK CCLK 8 100 ns Low to CS High t SSC Setup Time, CS 60 ns Transition to CCLK Low t SSCO Setup Time, CS 50 ns Transition to CCLK High t SDC Setup Time, CI (CI/O) 50 ns Data In to CCLK Low t HCD Hold Time, CCLK 50 ns Low to CI/O Invalid t DCD Delay Time, CCLK High Load = 100 pF plus 2 LSTTL Loads 80 ns to CI/O Data Out Valid −40˚C to +85˚C (TP3070-X) 100 ns www.national.com 13 |
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