AD5245

POWER-UP SEQUENCE

Since the ESD protection diodes limit the voltage compliance at

terminals A, B, and W (see Figure 44), it is important to power

powered unintentionally and may affect the rest of the user’s

circuit. The ideal power-up sequence is in the following order:

LAYOUT AND POWER SUPPLY BYPASSING

It is a good practice to employ compact, minimum lead length

layout design. The leads to the inputs should be as direct as

possible with a minimum conductor length. Ground paths

should have low resistance and low inductance.

Similarly, it is also a good practice to bypass the power supplies

with quality capacitors for optimum stability. Supply leads to the

device should be bypassed with disc or chip ceramic capacitors

of 0.01 µF to 0.1 µF. Low ESR 1 µF to 10 µF tantalum or

electrolytic capacitors should also be applied at the supplies to

minimize any transient disturbance and low frequency ripple

(see Figure 45). Note that the digital ground should also be

joined remotely to the analog ground at one point to minimize

the ground bounce.

AD5245

C1

C3

GND

10

µF

0.1

µF

+

Figure 45. Power Supply Bypassing

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN CONFIGURATION

A

B

AD0

SDA

1

2

3

4

5

8

7

6

W

GND

SCL

TOP VIEW

(Not to Scale)

AD5245

Figure 46.

PIN FUNCTION DESCRIPTIONS

Table 9.

Pin

Name

Description

1

W

W Terminal.

2

Positive Power Supply.

3

GND

Digital Ground.

4

SCL

Serial Clock Input. Positive edge triggered.

5

SDA

Serial Data Input/Output.

6

AD0

Programmable address bit 0 for multiple

package decoding.

7

B

B Terminal.

8

A

A Terminal.

Rev. 0 | Page 15 of 16