REV. A

AD9845B

–21–

Internal Power-On Reset Circuitry

After power-on, the AD9845B will automatically reset all inter-

nal registers and perform internal calibration procedures. This

takes approximately 1 ms to complete. During this time, normal

clock signals and serial write operations may occur. However,

serial register writes will be ignored until the internal reset opera-

tion is completed.

Grounding and Decoupling Recommendations

As shown in Figure 33, a single ground plane is recommended

for the AD9845B. This ground plane should be as continuous

as possible, particularly around Pins 25–39. This will ensure

that all analog decoupling capacitors provide the lowest possible

impedance path between the power and bypass pins and their

respective ground pins. All decoupling capacitors should be

located as close as possible to the package pins. A single clean

power supply is recommended for the AD9845B, but a separate

digital driver supply may be used for DRVDD (Pin 13). DRVDD

should always be decoupled to DRVSS (Pin 14), which should

be connected to the analog ground plane. Advantages of using

a separate digital driver supply include using a lower voltage

(2.7 V) to match levels with a 2.7 V ASIC and reducing digital

power dissipation and potential noise coupling. If the digital

outputs (Pins 1–12) must drive a load larger than 20 pF, buff-

ering is recommended to reduce digital code transition noise.

Alternatively, placing series resistors close to the digital out-

put pins may also help reduce noise.

Pin 37 on the AD9845A was called CML and required a 0.1

mF

bypass capacitor to ground. Pin 37 is not internally connected

on the AD9845B, and so the older AD9845A bypass capacitor

may be left in place. All NC pins are not internally connected on

the AD9845B and may be left floating or tied to ground.

36

35

34

33

32

31

30

29

28

27

26

25

13 14 15 16 17 18 19 20 21 22 23 24

1

2

3

4

5

6

7

8

9

10

11

12

37

48 47 46 45 44

39 38

43 42 41 40

PIN 1

IDENTIFIER

TOP VIEW

(Not to Scale)

AUX1IN

AVSS

AUX2IN

AVDD2

BYP3

NC

CCDIN

BYP2

BYP1

AVDD1

AVSS

AVSS

D0

D1

D2

D3

D4

D5

D6

D7

D8

(MSB) D11

AD9845B

3V

ANALOG SUPPLY

CCD SIGNAL

3V

ANALOG SUPPLY

12

DATA

OUTPUTS

3

SERIAL

INTERFACE

3V

ANALOG SUPPLY

8

CLOCK

INPUTS

3V

ANALOG SUPPLY

3V

DRIVER

SUPPLY

NC = INTERNALLY NOT CONNECTED

D9

D10

0.1

F

0.1

F

0.1

F

0.1

F

0.1

F

0.1

F

0.1

F

0.1

F

0.1

F

0.1

F

0.1

F

Figure 33. Recommended Circuit Configuration for CCD-Mode