output and then the successive-approximation encoding cy-

cle begins The 8-bit code is then loaded into a buffer and

coding delay will be approximately 165 ms (due to the trans-

mit filter) plus 125 ms (due to encoding delay) which totals

290 ms Any offset voltage due to the filters or comparator is

cancelled by sign bit integration

RECEIVE SECTION

The receive section consists of an expanding DAC which

drives a fifth order switched-capacitor low pass filter

clocked at 256 kHz The decoder is A-law and the 5th order

low pass filter corrects for the sin xx attenuation due to the

8 kHz samplehold The filter is then followed by a 2nd or-

section is unity-gain but gain can be added by using the

time slot the decoding cycle begins and 10 ms later the

decoder DAC output is updated The total decoder delay is

E

10 ms (decoder update) plus 110 ms (filter delay) plus

625 ms(

frame) which gives approximately 180 ms

RECEIVE POWER AMPLIFIERS

Two inverting mode power amplifiers are provided for direct-

ly driving a matched line interface transformer The gain of

anced 15 kX load The second power amplifier is internally

connected in unity-gain inverting mode to give 6 dB of signal

gain for balanced loads

Maximum power transfer to a 600X subscriber line termina-

tion is obtained by differentially driving a balanced trans-

Figure 4 A total

peak power of 156 dBm can be delivered to the load plus

termination

TP3069

A-Law

(Includes Even Bit Inversion)

1

0

101010

1

1

010101

0

1

010101

0

0

101010

4