TP3155 datasheet(2/10 Pages) NSC

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Absolute Maximum Ratings

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VCC Relative to GND

Voltage at Any Input

or Output

VCC a 03V to GND b03V

Operating Temperature Range

(Ambient)

25 Cto a125 C

Storage Temperature Range

(Ambient)

65 Cto a150 C

Maximum Lead Temperature

(Soldering 10 seconds)

300 C

ESD rating to be determined

DC Electrical Characteristics

Unless otherwise noted limits printed in BOLD characters are guaranteed for VCC e 50V g5% TA e 0 Cto a70 Cby

correlation with 100% electrical testing at TA e 25 C All other limits are assured by correlation with other production tests and

or product design and characterization Typicals specified at VCC e 50V TA e 25 C

Parameter

Conditions

Min

Typ

Max

Units

Input Voltage Levels

VIH Logic High

VIL Logic Low

Input Currents

All Inputs Except MODE

VIL k VIN k VIH

MODE

VIN e 0V

100

Output Voltage Levels

VOH Logic High

FSX and FSR Outputs IOH e 3 mA

VOL Logic Low

FSX and FSR Outputs IOL e 5 mA

TSX Output IOL e 5mA

Power Dissipation

BCLK e 2048 MHz

Operating Current

All Outputs Open-Circuit

Timing Specifications

Unless otherwise noted limits printed in BOLD characters are guaranteed for VCC e 50V g5% TA e 0 Cto a70 Cby

correlation with 100% electrical testing at TA e 25 C All other limits are assured by correlation with other production tests and

or product design and characterization Typicals specified at VCC e 50V TA e 25 C All timing parameters are measured at

VOH e 20V and VOL e 07V

See Definitions and Timing Conventions section for test methods information

Symbol

Parameter

Conditions

Min

Max

Units

tPC

Period of Clock

BCLK CLKC

480

tWCH

Width of Clock High

BCLK CLKC

160

tWCL

Width of Clock Low

BCLK CLKC

160

tSDC

Set-Up Time from DC to CLKC

tHCD

Hold Time from CLKC to DC

tSCC

Set-Up Time from CS to CLKC

tHCC

Hold Time from CLKC to CS

100

tSCHC

Set-Up Time from Channel Select to CLKC

tHCHC

Hold Time from Channel Select to CLKC

tDBF

Delay Time from BCLK Low to FSXR 0–3

CL e 50 pF

100

High or Low

tHSYNC

Hold Time from BCLK to Frame Sync

tSSYNC

Set-Up Time from Frame Sync to BCLK

100

tDTL

Delay to TSX Low

CL e 50 pF

140

tDTH

Delay to TSX High

RL e 1k to VCC

140

tRC tFC

Rise and Fall Time of Clock

BCLK CLKC

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