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FDMS8680 数据表(PDF) 16 Page - Texas Instruments |
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FDMS8680 数据表(HTML) 16 Page - Texas Instruments |
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16 / 27 page ![]() ( ) ( ) ( ) ( ) ( ) ( ) ( ) f f OUT OUT OUT OUT IN max IN max IND(ripple) SW SW IN max OUT max IN max V V V V V V 1 3 L I V I V - ´ - ´ = ´ = ´ ´ ´ ( ) ( ) ( ) f OUT OUT IN max TRIP IND(peak ) DS(on) SW IN max V V V V 1 I 8 R L V - ´ = + ´ ´ ´ ( ) f f OUT SW SW IND(ripple) V 10 mV 1 D 10 mV L L ESR 0.7 V I 0.7 V 70 ´ ´ - ´ ´ é ù é ù ´ ë û ë û = = = W é ù ë û ´ é ù é ù ë û ë û t SW t – Time 0 10 t SW x (1-D) V RIPPLE(FB) TPS51218 SLUS935B – MAY 2009 – REVISED FEBRUARY 2012 www.ti.com EXTERNAL COMPONENTS SELECTION Selecting external components is simple in D-CAP ™ mode. 1. Choose the inductor. The inductance value should be determined to give the ripple current of approximately 1/4 to 1/2 of maximum output current. Larger ripple current increases output ripple voltage and improves S/N ratio and helps stable operation. (6) The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak inductor current before saturation. The peak inductor current can be estimated in Equation 7. (7) 2. Choose the output capacitor(s). Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended. For loop stability, capacitance and ESR should satisfy Equation 2. For jitter performance, Equation 8 is a good starting point to determine ESR. where • D is the duty ratio • the output ripple down slope rate is 10 mV/tSW in terms of VFB terminal voltage as shown in Figure 18 • tSW is the switching period (8) Figure 18. Ripple Voltage Down Slope 16 Submit Documentation Feedback Copyright © 2009–2012, Texas Instruments Incorporated Product Folder Link(s): TPS51218 |
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