REVISION B 09/29/15

13

LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES

932SQL456 DATASHEET

Electrical Characteristics–REF14M

Test Clarification Table

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Notes

Output High Voltage

2.4

V

Output Low Voltage

0.55

V

Clock High Time

1.5V

27.5

ns

1

Clock Low Time

1.5V

27.5

ns

1

Edge Rate

Rising/Falling edge rate

1

1.9

4

V/ns

1,2

Duty Cycle

45

50.2

55

%

1

Jitter, Cycle to cycle

19

250

ps

1

See "Power Supply and Test Loads" page for termination circuits

Comments

TEST_SEL

HW PIN

TEST_MOD

E

HW PIN

TEST

ENTRY BIT

B6b6

REF/N or

HI-Z

B6b7

OUTPUT

0

X

0

X

NORMAL

10

X

0

HI-Z

10

X

1

REF/N

11

X

0

REF/N

11

X

1

REF/N

0X

1

0

HI-Z

0X

1

1

REF/N

B6b6: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)

B6b7: 1= REF/N, Default = 0 (HI-Z)

HW

SW

Power-up w/ TEST_SEL = 1 (>0.7V) to enter test

to disable test mode.

If TEST_SEL HW pin is 0 during power-up,

test mode can be selected through B6b6.

If test mode is selected by B6b6, then B6b7

is used to select HI-Z or REF/N

FS_B/TEST_Mode pin is not used.

Cycle power to disable test mode.