LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES

12

REVISION B 09/29/15

932SQL456 DATASHEET

Electrical Characteristics–PCI

Electrical Characteristics–Phase Jitter Parameters

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

Output High Voltage

2.4

V

Output Low Voltage

0.55

V

Clock High Time

1.5V

12

ns

1

Clock Low Time

1.5V

12

ns

1

Edge Rate

Rising/Falling edge rate

1

1.7

4

V/ns

1,2

Duty Cycle

45

50.6

55

%

1

Group Skew

496

550

ps

1

Jitter, Cycle to cycle

23

250

ps

1

See "Power Supply and Test Loads" page for termination circuits

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

IND.

LIMIT

UNITS

Notes

PCIe Gen 1

24.8

30

86

ps (p-p)

1,2,3,

6

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

0.54

0.7

3

ps

(rms)

1,2,6

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

2.2

2.6/3

3.1

ps

(rms)

1,2,6

PCIe Gen 3 Common Clock

(PLL BW of 2-4MHz. CDR =

10MHz)

0.46

0.6

1

ps

(rms)

1,2,4,

6

S

PCIe Gen 3 Separate

Reference no Spread (SRnS)

(PLL BW of 2-4MHz. CDR =

10MHz)

0.46

0.6

0.7

ps

(rms)

1,2,4,

6

QPI & SMI

(100MHz, 4.8Gb/s, 6.4Gb/s

12UI)

0.24

0.4

0.5

ps

(rms)

1,5,6

QPI & SMI

(100MHz, 8.0Gb/s, 12UI)

0.13

0.15

0.3

ps

(rms)

1,5,6

QPI & SMI

(100MHz, 9.6Gb/s, 12UI)

0.11

0.13

0.2

ps

(rms)

1,5,6

SAS 12G

0.84

1.1/1.2

1.3

ps

(rms)

1,5,6

Phase Jitter