LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES

8

REVISION B 09/29/15

932SQL456 DATASHEET

Functionality Tables

Clock AC Tolerances

Clock Periods–Outputs

932SQL456 Functionality

CPU

SRC

PCI

REF

NS_SAS

NS_SRC

DOT96

USB

100

100

33.33

14.318

100.00

96.00

48.00

MHz

932SQL456 Power Down Functionality

CKPWRGD#/PD

Differential

Outputs

Single-

ended

Outputs

Single-

ended

Outputs

w/Latch

1Low/Low

Low

Low

1

0

1. Single-ended outputs with a Latch will be Hi-Z until

the first application of CKPWRGD#.

Running

CPU, SRC

NS_SAS,

NS_SRC

PCI

DOT96

48MHz

REF

100

100

100

100

100

100

ppm

50

50

250

50

250

250

ps

0.00%

0.00%

0.00%

0

0.00%

0.00%

%

PPM tolerance

Cycle to Cycle Jitter

Spread

1 Clock

1us

0.1s

0.1s

0.1s

1us

1 Clock

-c2c jitter

AbsPer

Min

-SSC

Short-Term

Average

Min

- ppm

Long-Term

Average

Min

0 ppm

Period

Nominal

+ ppm

Long-Term

Average

Max

+SSC

Short-Term

Average

Max

+c2c jitter

AbsPer

Max

CPU,

SRC,

NS_SAS,

NS_SRC

100.000

9.94900

9.99900

10.00000

10.00100

10.05100

ns

1,2

PCI

33.333

29.74700

29.99700

30.00000

30.00300

30.25300

ns

1,2

DOT96

96.000

10.36563

10.41563

10.41667

10.41771

10.46771

ns

1,2

48MHz

48.000

20.58125

20.83125

20.83333

20.83542

21.08542

ns

1,2

REF

14.318

69.78429

69.83429

69.84128

69.84826

69.89826

ns

1,2

Notes

Measurement Window

Units

SSC OFF

Center

Freq.

MHz