Mode Definitions

DESCRIPTION

PIN NAME

MODE

S1

S0

MODE

OPERATION

0

L

L

WRITE

Input dataword and output

checkword

1

L

H

DIAGNOSTICS

Input various data words

against latched

checkwordoutput valid

error flags

2

H

L

READ

FLAG

Input dataword and output

error flags

3

H

H

CORRECT

Latched input data and

checkwordoutput

corrected data and

syndrome code

Pin Definitions

S0 S1

Control of EDAC mode see preceding

Mode Definitions

DB0 thru DB31 IO port for 32 bit dataword

CB0 thru CB6

IO port for 7 bit checkword Also output

port for the syndrome error code during

error correction mode

OEB0 thru

Dataword output buffer enable When high

OEB3

output buffers are at TRI-STATE Each pin

(DP8402A

controls 8 IO ports OEB0 controls DB0

DP8403)

thru DB7 OEB1 controls DB8 thru DB15

OEB2 controls DB16 thru DB23 and OEB3

controls DB24 thru DB31

LEDBO

Data word output Latch enable When high

(DP8402A

it inhibits input to the Latch Operates on all

DP8403)

32 bits of the dataword

OEDB

TRI-STATE control for the data IO port

(DP8404

When high output buffers are at

DP8405)

TRI-STATE

OECB

Checkword output buffer enable When

high the output buffers are in TRI-STATE

mode

ERR

Single error output flag a low indicates at

least a single bit error

MERR

Multiple error output flag a low indicates

two or more errors present

PCC Pin Definitions DP8402A

pin 1

pin 35

OECB

2

LEDBO

36

CB3

3

MERR

37

CB2

4

ERR

38

CB1

5

DB0

39

CB0

6

DB1

40

DB16

7

DB2

41

DB17

8NC

42

NC

9NC

43

NC

10

NC

44

DB18

11

DB3

45

DB19

12

DB4

46

DB20

13

DB5

47

DB21

14

OEBO

48

OEB2

15

DB6

49

DB22

16

DB7

50

DB23

17

GND

51

GND

18

GND

52

GND

19

DB8

53

DB24

20

DB9

54

DB25

21

OEB1

55

OEB3

22

DB10

56

DB26

23

DB11

57

DB27

24

DB12

58

DB28

25

DB13

59

NC

26

DB14

60

NC

27

NC

61

NC

28

NC

62

NC

29

NC

63

DB29

30

DB15

64

DB30

31

NC

65

DB31

32

CB6

66

S0

33

CB5

67

S1

34

CB4

68

TABLE I Write Control Function

Memory

EDAC

Control

DB Control

DB Output Latch

CB

Error Flags

Cycle

Function

S1

S0

Data IO

OEBn or

DP8402A DP8403

Check IO

Control

ERR

MERR

OEDB

LEDBO

OECB

Write

Generate

L

L

Input

H

X

Output

LH

H

check word

check bits

See Table II for details on check bit generation

Memory Write Cycle Details

During a memory write cycle the check bits (CB0 thru CB6)

are generated internally in the EDAC by seven 16-input pari-

ty generators using the 32-bit data word as defined in Table

2 These seven check bits are stored in memory along with

the original 32-bit data word This 32-bit word will later be

used in the memory read cycle for error detection and cor-

rection

3