SN74SSTVF16859

13BIT TO 26BIT REGISTERED BUFFER

WITH SSTL_2 INPUTS AND OUTPUTS

SCES429B − MARCH 2003 − REVISED FEBRUARY 2004

2

POST OFFICE BOX 655303

description/ordering information (continued)

All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are edge-controlled LVCMOS

circuits optimized for unterminated DIMM loads.

The SN74SSTVF16859 operates from a differential clock (CLK and CLK). Data are registered at the crossing

of CLK going high and CLK going low.

The device supports low-power standby operation. When RESET is low, the differential input receivers are

RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must

be held at a valid logic high or low level.

To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in

the low state during power up.

RGQ PACKAGE

(TOP VIEW)

Q7A

Q6A

Q5A

Q4A

Q3A

Q2A

Q1A

Q13B

Q12B

Q11B

Q10B

Q9B

Q8B

D10

D9

D8

D7

RESET

GND

CLK

CLK

D6

D5

D4

1

2

3

4

5

6

7

8

9

10

11

12

13

14

42

41

40

39

38

37

36

35

34

33

32

31

30

29

GND†

† The center die pad must be connected to GND.

FUNCTION TABLE

INPUTS

OUTPUT

RESET

CLK

CLK

D

OUTPUT

Q

H

↑

↓

H

H

H

↑↓

LL

H

L or H

L or H

X

Q0

L

X or

floating

X or

floating

X or

floating

L