8-OUTPUT CK420BQ DERIVATIVE

8

OCTOBER 28, 2016

9SQL4958 DATASHEET

Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Common Clocked

Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Separate

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

SPECIFICATION

LIMIT

UNITS NOTES

PCIe Gen 1

19

30

86

ps (p-p)

3

PCIe Gen 2 Low Band

10kHz < f < 1.5MHz

(PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz)

0.4

0.6

3

ps

(rms)

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

(PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz)

1.2

1.9

3.1

ps

(rms)

PCIe Gen 3

(PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz)

0.27

0.45

1

ps

(rms)

PCIe Gen 4

(PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz)

0.27

0.45

0.5

ps

(rms)

Phase Jitter,

PLL Mode

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

INDUSTRY

LIMIT

UNITS NOTES

SRIS

PCIe Gen 1

n/a

None

ps

(rms)

2, 7

SRIS

PCIe Gen 2

(PLL BW of 16MHz , CDR = 5MHz)

0.7

1.2

2

ps

(rms)

2

SRIS

PCIe Gen 3

(PLL BW of 2-4MHz, CDR = 10MHz)

0.5

0.65

0.7

ps

(rms)

2

SRIS

PCIe Gen 4

(PLL BW of 2-4MHz, CDR = 10MHz)

n/a

None

ps

(rms)

2, 7

Notes on PCIe Filter Phase Jitter Tables

architectures.

defined for the IR clock architecture. Widely accepted industry limits using widely accepted industry filters are used to populate this

table. There are no accepted filters or limits for IR clock architectures at PCIe Gen1 or Gen4 data rates

Phase Jitter, PLL

Mode