LM5122ZPWPR datasheet(21/51 Pages) TI1

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OUT

IN MIN

750ns

margin [V]

OUT

IN MIN

400ns

margin [V]

SYNCIN/RT

LM5122

fSYNC

LM5122, LM5122-Q1

www.ti.com

SNVS954G – FEBRUARY 2013 – REVISED MAY 2016

Product Folder Links: LM5122 LM5122-Q1

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Feature Description (continued)

Figure 24. Oscillator Synchronization Through a Resistor in Master1 Mode

In master2 and slave modes, this external synchronization clock should be directly connected to the RT pin and

always provided continuously. The internal oscillator frequency can be either of two times faster than switching

frequency or the same as the switching frequency by configuring the combination of FB and OPT pins (see

Table 1).

7.3.12 Maximum Duty Cycle

When operating with a high PWM duty cycle, the low-side N-channel MOSFET device is forced off each cycle.

This forced LO off-time limits the maximum duty cycle of the controller. When designing a boost regulator with

high switching frequency and high duty cycle requirements, a check should be made of the required maximum

duty cycle. The minimum input supply voltage which can achieve the target output voltage is estimated from

Equation 14 or Equation 15.

Use Equation 14 if VVCC is greater than 5.5 V or VVIN is greater than 6.0 V. For low voltage applications that do

not satisfy either of these conditions use Equation 15.

(14)

(15)

In normal operation, about 100 ns of margin is recommended.

7.3.13 Thermal Protection

Internal thermal shutdown circuitry is provided to protect the controller in the event the maximum junction

temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low-power shutdown

mode, disabling the output drivers, disconnection switch and the VCC regulator. This feature is designed to

prevent overheating and destroying the device.

7.4 Device Functional Modes

7.4.1 MODE Control (Forced PWM Mode and Diode Emulation Mode)

A fully synchronous boost regulator implemented with a high-side switch rather than a diode has the capability to

sink current from the output in certain conditions such as light load, overvoltage or load transient. The LM5122

can be configured to operate in either forced PWM mode or diode emulation mode.

In forced PWM mode (FPWM), reverse current flow in high-side N-channel MOSFET switch is allowed and the

inductor current conducts continuously at light or no load conditions. The benefit of the forced PWM mode is fast

light load to heavy load transient response and constant frequency operation at light or no load conditions. To

enable forced PWM mode, connect the MODE pin to VCC or tie to a voltage greater than 1.2 V. In FPWM mode,

reverse current flow is not limited.

In diode emulation mode, current flow in the high-side switch is only permitted in one direction (source to drain).

Turn-on of the high-side switch is allowed if CSP to CSN voltage is greater than 7 mV rising threshold of zero

current detection during low-side switch on-time. If CSP to CSN voltage is less than 6 mV falling threshold of

zero current detection during high-side switch on-time, reverse current flow from output to input through the high-

side N-channel MOSFET switch is prevented and discontinuous conduction mode of operation is enabled by

latching off the high-side N-channel MOSFET switch for the remainder of the PWM cycle. A benefit of the diode

emulation is lower power loss at light load conditions.

LM5122ZPWPR 数据表(PDF) 21 Page - Texas Instruments

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