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AS1372 数据表(PDF) 2 Page - ams AG |
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AS1372 数据表(HTML) 2 Page - ams AG |
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2 / 14 page ![]() www.austriamicrosystems.com/LDOs/AS1372 Revision 1.01 2 - 14 AS1372 Datasheet - P i n A s s i g n m e n t s 4 Pin Assignments Figure 2. Pin Assignments (Top View) Pin Descriptions Table 1. Pin Descriptions Pin Number Pin Name Description 1 VOUT Regulated Output Voltage. Bypass this pin with a capacitor to GND. 2 GND Ground. 3 EN Enable. Pull this pin to low to disable the device. This pin has an internal 1.6M Ω (typ.) pull-down resistor. 4 VBIAS Bias Supply Voltage. 2.5V to 5.5V, Bypass this pin with a capacitor to GND. 5 VIN Unregulated Input Voltage. 0.7V to 4.5V, VIN ≤ VBIAS, Bypass this pin with a capacitor to GND. 5 13 4 2 |
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