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June 2004

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HIGH SPEED:

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LOW POWER DISSIPATION:

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HIGH NOISE IMMUNITY:

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SYMMETRICAL OUTPUT IMPEDANCE:

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BALANCED PROPAGATION DELAYS:

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WIDE OPERATING VOLTAGE RANGE:

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PIN AND FUNCTION COMPATIBLE WITH

54 SERIES 75

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SPACE GRADE-1: ESA SCC QUALIFIED

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50 krad QUALIFIED, 100 krad AVAILABLE ON

REQUEST

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NO SEL UNDER HIGH LET HEAVY IONS

IRRADIATION

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DEVICE FULLY COMPLIANT WITH

SCC-9203-065

DESCRIPTION

The M54HC75 is an high speed CMOS 4 BIT D

technology.

It contains two groups of 2 bit latches controlled by

an enable input (G1

groups can be used in different circuits. Each latch

has Q and Q outputs (1Q - 4Q and 1Q - 4Q). The

data applied to the data input is transferred to the

Qand Q outputs when the enable input is taken

high and the outputs will follow the data input as

long as the enable input is kept high. When the

enable input is taken low, the information data

applied to the data input is retained at the outputs.

All inputs are equipped with protection circuits

against static discharge and transient excess

voltage.

M54HC75

RAD HARD 4 BIT D TYPE LATCH

PIN CONNECTION

ORDER CODES

PACKAGE

FM

EM

DILC

M54HC75D

M54HC75D1

FPC

M54HC75K

M54HC75K1

DILC-16

FPC-16

Rev. 1