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MM5035 数据表(PDF) 2 Page - National Semiconductor (TI) |
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MM5035 数据表(HTML) 2 Page - National Semiconductor (TI) |
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2 / 4 page ![]() Absolute Maximum Ratings If MilitaryAerospace specified devices are required please contact the National Semiconductor Sales OfficeDistributors for availability and specifications Supply Voltage 7 VDC Input Voltage 7 VDC Power Dissipation 750 mW Storage Temperature Range b 65 Cto a150 C Lead Temperature (Soldering 10 sec) 300 C Electrical Characteristics VDD e 5V g 5% TA e 0 Cto a70 C Parameter Conditions Min Typ Max Units Clock Input Logical ‘‘1’’ Input Voltage 22 V Logical ‘‘0’’ Input Voltage 08 V Data and Control Inputs Logical ‘‘1’’ Input Voltage 22 V Logical ‘‘0’’ Input Voltage 08 V Data Clock and Control Inputs Logical ‘‘1’’ Input Current VIN e 5V 50 m A Input Capacitance VIN e 25V 50 80 pF Outputs Logical ‘‘1’’ Output Voltage IOUT e 100 mA 24 28 V Logical ‘‘0’’ Output Voltage IOUT e 16 mA 025 04 V TRI-STATE Output Current VOUT e 5V b 50 m A VOUT e 0V 50 m A Supply Current 60 90 mA Timing Clock Frequency 0 30 MHz Clock Pulse Width High (Figure 1) 125 10000 ns Clock Pulse Width Low (Note 1) 125 % ns Output Rise and Fall Time (tr tf) (Figure 1) 40 50 ns Set-Up Time (Figure 1) 100 ns Hold Time (Figure 1) 0ns Output Enable Time (Figure 1) 185 ns Output Disable Time (Figure 1) 185 ns Clock Rise and Fall Time (Figure 1) 50 m s Output Delay (tPD) 80 185 ns Note 1 The clock input must be a low level for DC storage Minimum width assumes 10 ns tr and tf Recirculate and TRI-STATE Operation Recirculate is used to maintain data in the shift register after it has been loaded While the shift register is being loaded Recirculate must be at a logical ‘‘0’’ When the loading is completed Recirculate should be brought to a logical ‘‘1’’ This disables the data input and feeds the output of the last shift cell back to the input of the first shift cell for each of the 8 registers For the output to be in the TRI-STATE mode output-select should be at the logical ‘‘1’’ level 2 |
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