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STPMS2L-PUR 数据表(PDF) 5 Page - STMicroelectronics

部件名 STPMS2L-PUR
功能描述  Programmable chopper-stabilized low noise and low offset amplifier
PDF  36 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STPMS2L-PUR 数据表(HTML) 5 Page - STMicroelectronics

  STPMS2L-PUR Datasheet HTML 1Page - STMicroelectronics STPMS2L-PUR Datasheet HTML 2Page - STMicroelectronics STPMS2L-PUR Datasheet HTML 3Page - STMicroelectronics STPMS2L-PUR Datasheet HTML 4Page - STMicroelectronics STPMS2L-PUR Datasheet HTML 5Page - STMicroelectronics STPMS2L-PUR Datasheet HTML 6Page - STMicroelectronics STPMS2L-PUR Datasheet HTML 7Page - STMicroelectronics STPMS2L-PUR Datasheet HTML 8Page - STMicroelectronics STPMS2L-PUR Datasheet HTML 9Page - STMicroelectronics Next Button
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STPMS2
Introduction
DocID16525 Rev 5
5/36
1
Introduction
The STPMS2 is a device designed to measure electrical line parameters (voltage and
current) via analog signals from voltage sensors (current divider) and current sensors
(inductive Rogowski coil, current transformer or shunt resistors). The device is used
together with a digital signal processing circuit to implement an effective measuring system
for multi-phase power meters. The device consists of two analog measuring channels,
consisting of second-order sigma-delta modulators with an appropriate non-overlapping
control signal generator. The STPMS2 also includes a temperature compensated bandgap
reference voltage generator, a low drop supply voltage stabilizer and a minimal digital
circuitry that includes BIST (built-in self-test) structures. In a current signal processing
channel, a low-noise preamplifier is included in front of the sigma-delta converter. All
reference voltages (bandgap, AGND) are internally buffered to eliminate channel crosstalk.
The STPMS2 can operate in fast or low-power mode. In fast mode, a nominal clock
frequency of 4.1 or 4.9 MHz is applied to the clock input. In this mode, signal bandwidth is
specified between 0 and 4 kHz. In low-power mode, the nominal clock is four times slower
in order to reduce the power consumption of the circuit. In low-power mode, the quiescent
bias currents of the preamplifier and sigma-delta integrators are lowered and the signal
bandwidth is narrowed to the frequency bandwidth from 0 to 1 kHz.



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