TABLE I

Reg

RW

Description

(in HEX)

00

R

VENDOR ID

(100Bh)

02–3

R

DEVICE ID

(D001h)

04 – 5

RW

COMMAND REGISTER

The command register provides coarse control over a device’s ability to generate and

respond to PCI cycles

bit 0controls the response to the IO space accesses specified in the Base Address Register Default value is

determined by the ENABLE pin

1 Chip enable

0 Chip enable

bit 6

allows the controller to detect parity errors on the PCI bus and report these errors to the system

1 enable parity checking

0 disable parity checking (default)

bit 8allows the controller to detect system errors on the PCI bus and report these errors to the system

1 enable system error checking

0 disable system error checking (default)

06

RW

STATUS REGISTER

This register is used to record status information for PCI bus related events ‘‘Reads’’

from this register behaves normally However ‘‘write’’ to this register is slightly different respect to the ordinary

register This register can be reset but not set In order to reset this register a logical High need to write to the

corresponding bit For details please check P156 of the PCI specification 20 (April 30 1993)

bit 9 – 10 These bit encode the timing of DEVSEL

(read only)

00 fast

01 medium Default

bit 14 1 means system error

bit 15 This bit will be set by a device whenever that device detects a data parity error This bit is disabled when

parity error handling is disabled A logical one means detection of parity error Please check P 157 of the PCI

specification 20 (April 30 1993)

Reg

RW

Description

(in HEX)

08

R

REV ID

(00h)

09

R

PROGRAMMING INTERFACE

default is 00h

0A

R

SUB-CLASS CODE

default is 01h (means IDE controller)

0B

R

BASIC CLASS CODE

default is 01h (means mass storage)

0C – 0D

Not Used

0E

R

HEADER TYPE

default is 00h

10 – 13

RW

BASE ADDRESS REGISTERS 0

For Primary IDE Data Control Ports (Default 000001F0h – 000001F7h)

bit0 fixed to 1

bit1 fixed to 0

bit2 fixed to 0

14 – 17

RW

BASE ADDRESS REGISTERS 1

For Primary IDE Control Status Ports (Default 000003F6h) Note only ‘‘3F6’’

byte is accessible

bit0 fixed to 1

bit1 fixed to 0

18 – 1B

RW

BASE ADDRESS REGISTER 2

For Secondary IDE Data Control Ports (Default 00000170h – 0000177h)

bit0 fixed to 1

bit1 fixed to 0

bit2 fixed to 0

1C – 1F

RW

BASE ADDRESS REGISTER 3

For Secondary IDE Control Status Ports (Default 00000376h) Note only

‘‘376’’ byte is accessible

bit0 fixed to 1

bit1 fixed to 0

7