NAND01GW3A2AV1 datasheet(22/57 Pages) STMICROELECTRONICS

22 / 57 page

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

22/57

Read Memory Array

Each operation to read the memory area starts

with a pointer operation as shown in the Pointer

Operations section. Once the area (main or spare)

has been selected using the Read A, Read B or

Read C commands four bus cycles (for 512Mb

and 1Gb devices) or three bus cycles (for 128Mb

and 256Mb devices) are required to input the ad-

dress (refer to Table 6.) of the data to be read.

The device defaults to Read A mode after power-

up or a Reset operation.

When reading the spare area addresses:

■

A0 to A3 (x8 devices)

■

A0 to A2 (x16 devices)

are used to set the start address of the spare area

while addresses:

■

A4 to A7 (x8 devices)

■

A3 to A7 (x16 devices)

are ignored.

Once the Read A or Read C commands have

been issued they do not need to be reissued for

subsequent read operations as the pointer re-

mains in the respective area. However, the Read

B command is effective for only one operation,

once an operation has been executed in Area B

the pointer returns automatically to Area A and so

another Read B command is required to start an-

other read operation in Area B.

Once a read command is issued three types of op-

erations are available: Random Read, Page Read

and Sequential Row Read.

Random Read. Each time the command is is-

sued the first read is Random Read.

Page Read. After the Random Read access the

page data is transferred to the Page Buffer in a

time of tWHBH (refer to Table 21. for value). Once

the transfer is complete the Ready/Busy signal

goes High. The data can then be read out sequen-

tially (from selected column address to last column

address) by pulsing the Read Enable signal.

Sequential Row Read. After the data in last col-

umn of the page is output, if the Read Enable sig-

nal is pulsed and Chip Enable remains Low then

the next page is automatically loaded into the

Page Buffer and the read operation continues. A

Sequential Row Read operation can only be used

to read within a block. If the block changes a new

read command must be issued.

Refer to Figure 15. and Figure 16. for details of Se-

quential Row Read operations.

To terminate a Sequential Row Read operation set

the Chip Enable signal to High for more than tEHEL.

Sequential Row Read is not available when the

Chip Enable Don't Care option is enabled.

NAND01GW3A2AV1 数据表(PDF) 22 Page - STMicroelectronics

NAND01GW3A2AV1 数据表(HTML) 22 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57

数据表下载