DocID025389 Rev 2

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M41T01

Operation

24



Acknowledge

Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a

low level put on the bus by the receiver, whereas the master generates an extra

acknowledge related clock pulse (see Figure 5).

A slave receiver which is addressed is obliged to generate an acknowledge after the

reception of each byte. Also, a master receiver must generate an acknowledge after

the reception of each byte that has been clocked out of the slave transmitter.

The device that acknowledges has to pull down the SDA line during the acknowledge

clock pulse in such a way that the SDA line is a stable low during the high period of the

acknowledge related clock pulse. Of course, setup and hold times must be taken into

account. A master receiver must signal an end-of-data to the slave transmitter by not

generating an acknowledge on the last byte that has been clocked out of the slave. In

this case, the transmitter must leave the data line high to enable the master to generate

the STOP condition.

Figure 5. Acknowledgement sequence

AI00601

DATA OUTPUT

BY RECEIVER

DATA OUTPUT

BY TRANSMITTER

SCLK FROM

MASTER

START

CLOCK PULSE FOR

ACKNOWLEDGEMENT

12

89

MSB

LSB