| 数据搜索系统,热门电子元器件搜索 |
|
STM690 数据表(PDF) 25 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STM690 数据表(HTML) 25 Page - STMicroelectronics |
|
25 / 31 page ![]() 25/31 STM690/704/795/802/804/805/806 Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = VRST (max) to 5.5V; and VBAT = 2.8V (except where noted). 2. VCC supply current, logic input leakage, Watchdog functionality, Push-button Reset functionality, PFI functionality, state of RST and RST tested at VBAT = 3.6V, and VCC = 5.5V. The state of RST or RST and PFO is tested at VCC = VCC (min). Either VCC or VBAT can go to 0V if the other is greater than 2.0V. 3. VCC (min) = 1.0V for TA = 0°C to +85°C. 4. Tested at VBAT = 3.6V, VCC = 3.5V and 0V. 5. Guaranteed by design. 6. The leakage current measured on the RST pin (STM804/805) or RST pin (STM795) is tested with the reset output not asserted (output high impedance). 7. Not valid for STM795/804/805 (open drain). 8. When VBAT > VCC > VSW, VOUT remains connected to VCC until VCC drops below VSW. 9. When VSW > VCC > VBAT, VOUT remains connected to VCC until VCC drops below the battery voltage (VBAT) – 75mV. 10. The reset threshold tolerance is wider for VCC rising than for VCC falling due to the 10mV (typ) hysteresis, which prevents internal oscillation. Reset Thresholds VRST (10) Reset Threshold STM690T/ 704T/795T/ 805T VCC Falling 3.00 3.075 3.15 V VCC Rising 3.00 3.085 3.17 V STM802T/ 804T/806T VCC Falling 3.00 3.075 3.12 V VCC Rising 3.00 3.085 3.14 V STM690S/ 704S/795S/ 805S VCC Falling 2.85 2.925 3.00 V VCC Rising 2.85 2.935 3.02 V STM802S/ 804S/806S VCC Falling 2.88 2.925 3.00 V VCC Rising 2.88 2.935 3.02 V STM690R/ 704R/795R/ 805R VCC Falling 2.55 2.625 2.70 V VCC Rising 2.55 2.635 2.72 V STM802R/ 804R/806R VCC Falling 2.59 2.625 2.70 V VCC Rising 2.59 2.635 2.72 V trec RST Pulse Width VCC < 3.6V 140 200 280 ms Push-button Reset Input (STM704/806) tMLMH tMR MR Pulse Width 100 20 ns tMLRL tMRD MR to RST Output Delay 60 500 ns Watchdog Timer (NOT available on STM704/795/806) tWD Watchdog Timeout Period VRST (max) < VCC < 3.6V 1.12 1.60 2.24 s WDI Pulse Width VRST (max) < VCC < 3.6V 100 20 ns Chip-Enable Gating (STM795 only) E-to-ECON Resistance VCC = VRST (max) 46 Ω E-to-ECON Propagation Delay VCC = VRST (max) 27 ns Reset-to-ECON High Delay 10 µs ISC ECON Short Circuit Current VCC = 3.6V, Disable Mode, ECON = 0V 0.1 0.75 2.0 mA Sym Alter- native Description Test Condition(1) Min Typ Max Unit |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |