December 1998

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AN925

APPLICATION NOTE

Time Update in ST’s TIMEKEEPER Devices

Figure 1 shows how the non-volatile, static memory array and the quartz controlled clock oscillator, of

TIMEKEEPER devices from STMicroelectronics, are interconnected through the clock registers. The clock

registers are mapped into the memory array (please see the data sheet for the precise mapping) as 8 or

16 BYTEWIDE BIPORT memory cells. The time data in these memory cells are updated from the clock

side (the system side) and are made available to the user side within the user’s finest time resolution.

However, the user’s finest time resolution is one second, so this leaves plenty of scope for variability (of

the order of several milliseconds) between one update and the next. Since this variability might be notice-

able to some applications (for example, those that poll the time registers regularly, or those that use an

alarm function that is triggered once per second), this document sets out to explain the nature of the var-

iability, to make it more predictable to the applications designer.

Figure 1. Internal Architecture of an ST TIMEKEEPER Device

AI02482

LITHIUM

CELL

OSCILLATOR AND

CLOCK CHAIN

VPFD

VCC

VSS

32,768 Hz

CRYSTAL

VOLTAGE SENSE

AND

SWITCHING

CIRCUITRY

8, 16 x 8

TIMEKEEPER

REGISTERS

SRAM ARRAY

A0-AX

DQ0-DQ7

POWER

WDI

E

W

G

BATTERY LOW

IRQ/FT

RST

INTEGRATED BATTERY

CRYSTAL AND

SNAPHAT