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DS3678 数据表(PDF) 3 Page - National Semiconductor (TI) |
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DS3678 数据表(HTML) 3 Page - National Semiconductor (TI) |
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3 / 6 page ![]() Switching Characteristics VCC 5V TA 25 C (Note 4) Symbol Parameter Conditions Min Typ Max Units tSg Storage Delay Negative Edge (Figure 1) CL 50 pF 5 7 ns CL 500 pF 9 12 ns tS’ Storage Delay Positive Edge (Figure 1) CL 50 pF 6 8 ns CL 500 pF 9 13 ns tF Fall Time (Figure 1) CL 50 pF 5 8 ns CL 500 pF 22 35 ns tR Rise Time (Figure 1) CL 50 pF 6 9 ns CL 500 pF 22 35 ns tZL Delay from Output Control Input to Logical ‘‘0’’ CL 50 pF RL 2kX to VCC 10 15 ns Level (from High Impedance State) (Figure 2) tZH Delay from Output Control Input to Logical ‘‘1’’ CL 50 pF RL 2kX to GND 815 ns Level (from High Impedance State) (Figure 2) tLZ Delay from Output Control Input to High Impedance CL 50 pF RL 400X to VCC 15 25 ns State (from Logical ‘‘0’’ Level) (Figure 3) tHZ Delay from Output Control Input to High Impedance CL 50 pF RL 400X to GND 10 25 ns State (from Logical ‘‘1’’ Level) (Figure 3) tSg Propagation Delay to Logical ‘‘0’’ Transition When CL 50 pF (Figure 1) 12 15 ns Select Selects A tS’ Propagation Delay to Logical ‘‘1’’ Transition When CL 50 pF (Figure 1) 14 17 ns Select Selects A tSg Propagation Delay to Logical ‘‘0’’ Transition When CL 50 pF (Figure 1) 16 20 ns Select Selects B tS’ Propagation Delay to Logical ‘‘1’’ Transition When CL 50 pF (Figure 1) 14 20 ns Select Selects B Schematic Diagram TLF7506 3 DS1648DS3648 only 3 |
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