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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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MM74HC299 数据表(PDF) 4 Page - National Semiconductor (TI) |
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MM74HC299 数据表(HTML) 4 Page - National Semiconductor (TI) |
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4 / 6 page  AC Electrical Characteristic (Continued) CL 50 pF tr tf 6 ns unless otherwise specified TA 25 C 74HC 54HC Symbol Parameter Conditions VCC TA b40 to 85 CTA b55 to 125 C Units Typ Guaranteed Limits tPZH tPZL Maximum Output Enable RL 1kX CL 50 pF 20V 70 160 200 225 ns CL 150 pF 20V 90 220 275 310 ns CL 50 pF 45V 22 32 40 45 ns CL 150 pF 45V 30 44 55 62 ns CL 50 pF 60V 19 28 34 38 ns CL 150 pF 60V 24 47 47 51 ns tPHZ tPLZ Maximum Output Disable Time RL 1kX 20V 70 160 200 225 ns CL 50 pF 45V 22 32 40 45 ns 60V 19 28 34 38 ns tS Minimum Setup Time 20V 100 125 140 ns Data Select SL or SR 45V 20 25 28 ns 60V 17 21 25 ns tH Minimum Hold Time 20V 0 0 0 ns Data Select SL or SR 45V 0 0 0 ns 60V 0 0 0 ns tREM Minimum Clear Removal Time 20V 10 10 10 ns 45V 10 10 10 ns 60V 10 10 10 ns tW Minimum Pulse Width 20V 100 125 140 ns Clock and Clear 45V 20 25 28 ns 60V 17 21 25 ns tr tf Maximum Input Rise 20V 1000 1000 100 ns and Fall Time 45V 500 500 500 ns 60V 400 400 400 ns tTHL tTLH Maximum Output Rise 20V 60 75 90 ns and Fall Time Clock 45V 12 15 18 ns 60V 10 13 15 ns CPD Power Dissipation Outputs Enabled 240 pF Capacitance Outputs Disabled 110 pF CIN Maximum Input Capacitance 5 10 10 10 pF Capacitance COUT Maximum TRI-STATE 15 20 20 20 pF Output Capacitance Note 5 CPD determines the no load dynamic power consumption PD CPD VCC2 faICC VCC and the no load dynamic current consumption IS CPD VCC faICC Function Table Inputs InputsOutputs Outputs Function Output Mode Clear Select Control Clock Serial AQA BQB CQC DQD EQE FQF GQG HQH QA’ QH’ S1 S0 G1 G2 SL SR Clear LX L L L X X X L L L L L L L L L L LL X L L X X X L L L L L L L L L L Hold HL L L L X X X QA0 QB0 QC0 QD0 QE0 QF0 QG0 QH0 QA0 QH0 HX X L L L or H X X QA0 QB0 QC0 QD0 QE0 QF0 QG0 QH0 QA0 QH0 Shift Right HL H L L u XH H QAn QBn QCn QDn QEn QFn QGn HQGN HL H L L u XL L QAn QBn QCn QDn QEn QFn QGn LQGN Shift Left HH L L L u HX QBn QCn QDn QEn QFn QGn QHn HQBn H HH L L L u LX QBn QCn QDn QEn QFn QGn QHn LQBn L Load H H H X X u XX a b c d e f g h a h When one or both controls are high the eight inputoutput terminals are disabled to the high-impedance state however sequential operation or clearing of the register is not affected 4 |
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