CS5522-AS datasheet(28/56 Pages) CIRRUS

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CS5521/22/23/24/28

DS317F2

2.2.7.1 Latch Outputs

The A1-A0 pins mimic the latch output, D23/D11-

D22/D10, bits of the channel-setup registers. A1-A0

can be used to control external multiplexers and oth-

er logic functions outside the converter. The outputs

can sink or source at least 1 mA, but it is recom-

mended to limit drive currents to less than 20

µA to

reduce self-heating of the chip. These outputs are

powered from VA+, hence, their output voltage for

a logic 1 will be limited to the VA+ supply voltage.

2.2.7.2 Channel Select Bits

The channel select, CS1-CS0, bits are used to de-

termine which physical input channel will be used

when a conversion is performed with a particular

Setup.

2.2.7.3 Output Word Rate Selection

The word rate, WR2-WR0, bits of the channel-set-

up registers set the output conversion word rate of

the converter when a conversion is performed with

a particular Setup. The word rates indicated in

Table 3 assume a master clock of 32.768 kHz, and

scale linearly when using other master clock fre-

quencies. Upon reset the converter is set to operate

with an output word rate of 15.0 Hz.

2.2.7.4 Gain Bits

The gain bits, G2-G0, of the channel-setup regis-

ters set the full scale differential input range for the

ADC when a conversion is performed with a partic-

ular Setup. The input ranges in the table assume a

2.5 V reference voltage, and scale linearly when

using other reference voltages.

2.2.7.5 Unipolar/Bipolar Bit

The unipolar/bipolar bit is used to determine the

type of conversion, unipolar/bipolar, that will be

performed with a particular Setup.

2.2.8 Configuration Register

The configuration register is 24-bits long. The fol-

lowing subsections detail the bits in the configura-

tion register. Table 4 summarizes the configuration

2.2.8.1 Chop Frequency Select

The chop frequency select (CFS1-CFS0) bits are

used to set the rate at which the instrumentation

amplifier’s chop switches modulate the input sig-

nal. The 256 Hz rate is desirable as it provides the

lowest input CVF (sampling) current, <300 pA

over -40 to 85 C. The higher rates can be used to

eliminate modulation/aliasing effects as the fre-

quency of the input signal increases.

2.2.8.2 Conversion/Calibration Control Bits

The conversion/calibration control bits in the con-

figuration register are used to control the particular

type of conversion required for the users applica-

tions. In short, the depth pointer (DP3-DP0) bits

determine the number of Setups that will be refer-

enced when conversions are performed. The multi-

ple conversion (MC) bit instructs the converter to

perform conversions on the number of Setups in the

channel-setup registers which are referenced by the

depth pointer bits. The converter begins with

Setup1 and moves sequentially through the Setups

in this mode. The Loop (LP) bit instructs the con-

verter to continuously perform conversions until a

stop command is sent to the converter. The read

convert (RC) bit instructs the converter to wait until

the conversion data is read before performing the

next conversion or set of conversions.

2.2.8.3 Power Consumption Control Bits

The CS5522/24/28 accommodate four power con-

sumption modes: normal, low power, standby, and

sleep. The CS5521/23 accommodate three power

consumption modes: normal, standby, and sleep.

The normal (default) mode is entered after a power-

on-reset. In normal mode, the CS5522/24/28 typi-

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