STCD22X0 datasheet(12/39 Pages) STMICROELECTRONICS

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Device operation

STCD22x0, STCD23x0, STCD24x0

12/39

Doc ID 15400 Rev 2

Device operation

3.1

Operation

The STCD22x0, STCD23x0 and STCD24x0 are 2, 3 or 4 buffered clock distribution circuits.

They accept the clock (either square wave or sine wave) input from an external clock source

and send 2, 3 or 4 buffered rail-to-rail (0 V to VTCXO) square wave outputs to different

devices. A 1.8 V, high PSRR LDO (VTCXO) is also integrated in the STCD22x0, STCD23x0

and STCD24x0 which can be used as a voltage supply for the external master clock source

(such as a TCXO). This LDO stops the current increase through PMOS when the load

current reaches the limit value of the current-limit protection circuit. When the load current

falls below the limit values, the current limit is released.

Each of the STCD22x0, STCD23x0 and STCD24x0 clock outputs can be enabled

individually. If the device connected to the output is in standby, and does not require a clock,

the buffered output can be disabled to save power consumption. Once the buffered output is

disabled, it is pulled down to GND internally. If all the devices connected are in standby, the

STCD22x0, STCD23x0 and STCD24x0 are also put into standby mode (the internal LDO is

also shut down) for further power consumption savings. All of the output enable signals are

logic ORed with an open drain output (MCREQ) to control the output of the source clock. If

the output clock is required by at least one device, the LDO wakes up and the MCREQ

activates the clock source. The truth table for enable signals, the master clock request signal

and the VTCXO is given in

Table 5. The truth table for enable signals, output clock signals

and the master clock is given in

Table 6.

The STCD22x0, STCD23x0 and STCD24x0 have the master clock input detector integrated.

If the input master clock peak-to-peak voltage is below the minimum specified level, even if

the outputs are enabled, there are no clock outputs and STCD22x0, STCD23x0 and

STCD24x0 enter standby mode. Once the master clock peak-to-peak voltage level reaches

the minimum value, the output clocks are asserted if the enable pins are active.

Table 5 and 6, the enable signals are active high and the MC

REQ is active low. These

enable signals can be active high or active low. The enable polarity is described in

Section 3.2: Enable polarity. Customers can select different polarity options for different

applications. Contact the STMicroelectronics local sales office for availability.

Note:

"0" means logic low which disables the clock output and "1" means logic high which enables

the clock output. This is an active high truth table. Refer to Section 3.2: Enable polarity for

the detailed enable active high/low options.

Table 5.

Truth table for clock enable (EN1-4), master clock request (MCREQ) and

VTCXO

EN1

EN2

EN3

EN4

MCREQ

VTCXO

GND

1.8 V

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