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TS4621E 数据表(PDF) 9 Page - STMicroelectronics |
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TS4621E 数据表(HTML) 9 Page - STMicroelectronics |
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9 / 32 page  TS4621E Electrical characteristics Doc ID 022201 Rev 1 9/32 Figure 2. SCL and SDA timing diagram Figure 3. Start and stop condition timing diagram Table 7. Timing characteristics of the I²C interface for I²C interface signals over recommended operating conditions (unless otherwise specified) Symbol Parameter Min. Typ. Max. Unit fSCL Frequency, SCL 400 kHz td(H) Pulse duration, SCL high 0.6 µs td(L) Pulse duration, SCL low 1.3 µs tst1 Setup time, SDA to SCL 100 ns th1 Hold time, SCL to SDA 0 ns tf Bus free time between stop and start condition 1.3 µs tst2 Setup time, SCL to start condition 0.6 µs th2 Hold time, start condition to SCL 0.6 µs tst3 Setup time, SCL to stop condition 0.6 µs SCL SDA t d(H) t d(L) t st1 t h1 AM06113 AM06114 t st3 SCL SDA t st2 Start condition Stop condition t h2 t f |
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