SIL60C2 Data Sheet

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SIL60C2 DS 25Mar2015

Mating Connectors

Mechanical Drawings

7.20

MAX

MAX

2.54

TYP

3.05

.120

.100

.283

.548 MAX

13.92 MAX

TYP

2.54

.100

.090

2.29

.118

3

PCB REF

1.57±0.15

.062±.006

.197 MAX

5 MAX

37

2

38

1

7001153-JPLUTO

SCALE: 2 = 1

SIZE

CAD FILE:

DWG. NO.

B

TOMAHAWK, TLA, VERTICAL

APPROVALS

DRAWN

ENGINEER

UNLESS OTHERWISE SPECIFIED

DIMENSIONS ARE IN INCHES

TOLERANCES:

HOLE TOLERANCE:

2 PLACE

3 PLACE

ANGLES

.03

MATERIAL

FINISH

NA

NA

1

2

3

4

5

6

7

8

PH. 952-941-1100

PROJECT USED ON:

7091153-JPLUTO

TITLE:

DELL TOMAHAWK

EDEN PRAIRIE, MN 55433

ARTESYN TECHNOLOGIES

PROJECTION

ANGLE

DATE

.015

THIRD

1

.005

D. TETZLAFF

D. TETZLAFF

28AUG06

28AUG06

DETACHED LIST

NOTE:

1. 9300161-0000 PACKAGING AND MATERIAL HANDLING PROCEDURE.

2. COSMETIC AND WORKMANSHIP PER 9300152-0000.

3. LABEL SHOWN FOR REFERENCE PLACEMENT ONLY.

.025±.001

SQ PIN

0.64±0.03

1.980±.020

50.29±0.51

.780±.020

19.81±0.51

.625±.010 REF

15.88±0.25

LABEL

PRODUCT

2

1

38

37

RECOMMENDED MOTHERBOARD FOOTPRINT

MODULE OUTLINE

TYP

.044 TYP

2.080

.640

.140

1.800

TYP

.111

.100

.100 TYP

HEATSINK ASSEMBLY NOTES

APPLY LIQUIBOND BETWEEN THESE

SEMICONDUCTORS AND HEATSINK SURFACES,

STENCIL APPLICATION ACCEPTABLE.

APPLY GAPFILLER

ON BACKSIDE OF IC

TO FILL BETWEEN

HEATSINK ANDPCB

Pin Assignments

Pin

Function

Pin

Function

Pin

Function

1

VID0

14

Vin

27

Vout

2

Viout*

15

Ground

28

Vout

3

VID1

16

Ground

29

Ground

4

Power Good

17

Vout

30

Ground

5

RS-

18

Vout

31

Ground

6

RS+

19

Vout

32

Ground

7

Open

20

Vout

33

Vout

8

Enable

21

Ground

34

Vout

9

Ground

22

Ground

35

Vout

10

Ground

23

Ground

36

Vout

11

Vin

24

Ground

37

Ground

12

Vin

25

Vout

38

Ground

13

Vin

26

Vout

*Viout is a current monitoring pin. 31 mV / A, ±15% tolerance.