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HT9B95 数据表(PDF) 16 Page - Holtek Semiconductor Inc

部件名 HT9B95
功能描述  RAM Mapping 39횞8 / 43횞4 LCD Driver
PDF  32 Pages
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制造商  HOLTEK [Holtek Semiconductor Inc]
网页  http://www.holtek.com
标志 HOLTEK - Holtek Semiconductor Inc

HT9B95 数据表(HTML) 16 Page - Holtek Semiconductor Inc

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Rev. 1.10
16
November 25, 2015
HT9B95A/B/G
• Display RAM Page Write Operation
AfteraSTARTconditiontheslaveaddresswith
aR/W bitisplacedonthebus followedwith
thespecifieddisplayRAMRegisterAddressof
whichthecontentsarewrittenintotheinternal
addresspointer.Thedatatobewrittenintothe
memorywillbetransmittednext.Theinternal
addresspointerwillbeincrementedby1after
a8-bitdataisshiftedin.Thentheacknowledge
clockpulsewillbereceivedafteran8-bitdatais
shifted.Aftertheinternaladdresspointreachesthe
maximumavailableaddress,22H,15Hor26H,the
addresspointerwillberesetto00H.Itisstrongly
recommendedtowritethedisplayRAMdatafrom
address00Htomaximumavailableaddressusing
theDisplayRAMPageWriteOperation.
Part No. Duty Maximum Available Address
HT9B95A
1/8
22H
HT9B95B
HT9B95G
1/4
15H
1/8
26H
Display RAM Maximum Available Address
Read Operation
• Display RAM Read Operation
The master reads the display RAM data after
setting the slave address. Following the R/W
bit(=”0”)isanacknowledgebitandtheregister
addressbytewhichiswrittentotheinternaladdress
pointer.Afterthestartaddressofthereadoperation
hasbeenconfigured,anotherSTARTconditionand
theslaveaddresstransferredonthebusfollowed
bytheR/Wbit(=”1”).ThentheMSBofthedata
whichwasaddressedistransmittedfirstonthe
I2Cbus.Theaddresspointerisonlyincremented
by1afterthereceptionofanacknowledgeclock.
Afterreachingthemaximumavailableaddress,the
addresspointerwillberesetto00H.TheCbitin
theregisteraddressbytecanbesetto“1”or“0”.
Thisreadoperationwillcontinueuntilthemaster
sendsaSTOPcondition.Themaximumavailable
addressissummarizedintheabovesection.
Slave Address
ACK
S
0
1
1
1
1
1
0
0
ACK
Address n
ACK
Data byte
P
D7
D6
D5
D4
D3
D2
D1
D0
Data byte
D7
D6
D5
D4
D3
D2
D1
D0
ACK
ACK
Data byte
D7
D6
D5
D4
D3
D2
D1
D0
nth data
ACK
RAM Address byte
A0
A1
A2
A3
A4
A5
0
0
( n+1)th data
Nth data
W
R/
C bit
I2C Interface N Bytes Display RAM Data Write Operation
ACK
Write
P
Slave Address
S
0
1
1
1
1
1
0
0
Data byte
NACK
D7
D6
D5
D4
D3
D2
D1
D0
1st data
Data byte
ACK
P
D7
D6
D5
D4
D3
D2
D1
D0
Nth data
Data byte
D7
D6
D5
D4
D3
D2
D1
D0
2nd data
ACK
ACK
Device Address
Read
S
0
1
1
1
1
1
0
1
ACK
RAM Address byte
A0
A1
A2
A3
A4
A5
0
C
W
R/
C bit
W
R/
Display RAM Read Operation



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