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TUSB8043RGCT 数据表(PDF) 10 Page - Texas Instruments |
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TUSB8043RGCT 数据表(HTML) 10 Page - Texas Instruments |
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10 / 59 page  td2 GRSTz VDD33 VDD MISC_IO td1 tsu_io thd_io 10 TUSB8043 SLLSEW4 – JUNE 2017 www.ti.com Product Folder Links: TUSB8043 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated (1) Applies to external inputs and bidirectional buffers. (2) Applies to external outputs and bidirectional buffers. (3) Applies to GRSTz. (4) Applies to pins with internal pullups/pulldowns. (5) Applies to external input buffers. 7.5 Electrical Characteristics, 3.3-V I/O over operating free-air temperature range (unless otherwise noted) PARAMETER OPERATION TEST CONDITIONS MIN TYP MAX UNIT VIH High-level input voltage(1) VDD33 2 VDD33 V VIL Low-level input voltage(1) VDD33 0 0.8 V VI Input voltage 0 VDD33 V VO Output voltage(2) 0 VDD33 V tt Input transition time (trise and tfall) 0 25 ns Vhys Input hysteresis(3) 0.13 x VDD33 V VOH High-level output voltage VDD33 IOH = -4 mA 2.4 V VOL Low-level output voltage VDD33 IOL = 4 mA 0.4 V IOZ High-impedance, output current(2) VDD33 VI = 0 to VDD33 ±20 µA IOZP High-impedance, output current with internal pullup or pulldown resistor(4) VDD33 VI = 0 to VDD33 ±250 µA II Input current(5) VDD33 VI = 0 to VDD33 ±15 µA RPD Internal pull-down resister 13.5 19 27.5 KΩ RPU Internal pull-up resistor 14.5 19 25 KΩ (1) An active reset is required if the VDD33 supply is stable before the VDD11 supply. This active Reset shall meet the 3ms power-up delay counting from both power supplies being stable to the de-assertion of GRSTz. (2) There is no power-on relationship between VDD33 and VDD unless GRSTz is only connected to a capacitor to GND. Then VDD must be stable minimum of 10 µs before the VDD33. (3) MISC pins sampled at de-assertion of GRSTz: BATEN[4:1], AUTOENz, FULLPWRMGMTz, GANGED, SMBUSz, and PWRCTL_POL. 7.6 Timing Requirements, Power-Up PARAMETER DESCRIPTION MIN TYP MAX UNIT td1 VDD33 stable before VDD stable(1) See (2) ms td2 VDD and VDD33 stable before de-assertion of GRSTz 3 ms tsu_io Setup for MISC inputs(3) sampled at the de-assertion of GRSTz 0.1 µs thd_io Hold for MISC inputs(3) sampled at the de-assertion of GRSTz 0.1 µs tVDD33_RAMP VDD33 supply ramp requirements 0.2 100 ms tVDD_RAMP VDD supply ramp requirements 0.2 100 ms Figure 1. Power-Up Timing Requirements |
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