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R5F11BLE 数据表(PDF) 13 Page - Renesas Technology Corp |
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R5F11BLE 数据表(HTML) 13 Page - Renesas Technology Corp |
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13 / 143 page  RL78/G1F 1. OUTLINE R01DS0246EJ0110 Rev. 1.10 Page 13 of 140 Aug 12, 2016 (2/2) The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution not is issued by emulation with the in-circuit emulator or on-chip debug emulator. Item 24-pin 32-pin 36-pin 48-pin 64-pin R5F11B7x (x = C, E) R5F11BBx (x = C, E) R5F11BCx (x = C, E) R5F11BGx (x = C, E) R5F11BLx (x = C, E) Clock output/buzzer output 2 2 2 2 2 • 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fMAIN = 20 MHz operation) 8/10-bit resolution A/D converter 8 channels 13 channels 15 channels 17 channels 17 channels 8-bit D/A converter 1 channel 2 channels Comparator 2 channels Programmable gain amplifier (PGA) 1 channel Serial interface [24-pin, 32-pin, 36-pin products] • CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel • CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel • CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel [48-pin products] • CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I2C:2 channels • CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel • CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels [64-pin products] • CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 2 channels • CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels • CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels I2C bus 1 channel 1 channel 1 channel 1 channel 1 channel Data transfer controller (DTC) 30 sources 32 sources 31 sources 32 sources 33 sources Event link controller (ELC) Event input 21 21 21 22 22 Event trigger output 9 10 101010 Vectored interrupt sources Internal 25 25 25 25 25 External 9 11 101213 Key interrupt ——— 6 8 Reset • Reset by RESET pin • Internal reset by watchdog timer • Internal reset by power-on-reset • Internal reset by voltage detector • Internal reset by illegal instruction execution Note • Internal reset by RAM parity error • Internal reset by illegal-memory access Power-on-reset circuit • Power-on-reset: 1.51 ±0.04 V (TA = −40 to +85°C) 1.51 ±0.06 V (TA = −40 to +105°C) • Power-down-reset: 1.50 ±0.04 V (TA = −40 to +85°C) 1.50 ±0.06 V (TA = −40 to +105°C) Voltage detector [TA = −40 to +85°C] • Rising edge: 1.67 ±0.03 V to 4.00 ±0.08 V (14 stages) • Falling edge: 1.63 ±0.03 V to 3.98 ±0.08 V (14 stages) [TA = −40 to +105°C (G: Industrial applications)] • Rising edge: 2.61 ±0.1 V to 4.06 ±0.16 V (8 stages) • Falling edge: 2.55 ±0.1 V to 3.98 ±0.15 V (8 stages) On-chip debug function Provided Power supply voltage VDD = 1.6 to 5.5 V (TA = −40 to +85°C) VDD = 2.4 to 5.5 V (TA = −40 to +105°C) Operating ambient temperature TA = −40 to +85°C (A: Consumer applications), TA = −40 to +105°C (Industrial applications), |
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