ST6380B1 datasheet(38/82 Pages) STMICROELECTRONICS

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ST6380, ST6381, ST6382, ST6383, ST6388, ST6389

SERIAL PERIPHERAL INTERFACE (Cont’d)

4.3.2 S-BUS/I2C BUS Timing Diagrams

The clock of the S-BUS/I2C BUS of the ST638x

SPI (single master only) has a fixed bus clock fre-

quency of 62.5KHz. All the devices connected to

the bus must be able to follow transfers with fre-

quencies up to 62.5KHz, either by being able to

transmit or receive at that speed or by applying the

clock synchronization procedure which will force

the master into a wait state and stretch low peri-

ods.

Figure 26. S-BUS Timing Diagram

Note: The third pin, SEN, should be high; it is not used in the I2C BUS. Logically SDA is the AND of the

S-BUS SDA and SEN.)

VA00454

SCL

SEN (TRANSMIT)

SDA (TRANSMIT)

SDA pulled low by receiver

if acknowledged.

^ ^ ^

SDA pulled low by SPI Peripheral.

SDA (RECEIVE)

SEN (RECEIVE)

SEN (START)

SDA (START)

^ ^ ^

SDA pulled low by receiver

if acknowledged.

SEN (STOP)

SDA (STOP)

^ ^ ^

SDA pulled low by receiver if acknowledge. If in receive then there

will be no ACK. by the SPI.

SCL

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