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VIPER16

Layout guidelines and design recommendations

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Layout guidelines and design recommendations

A proper printed circuit board layout is essential for correct operation of any switch-mode

converter and this is true for the VIPer16 as well. Also some trick can be used to make the

design rugged versus external influences.

Careful component placing, correct traces routing, appropriate traces widths and

compliance with isolation distances are the major issues.

The main reasons to have a proper PCB routing are:

–

Provide a noise free path for the signal ground and for the internal references,

ensuring good immunity against external noises and switching noises

–

Minimize the pulsed loops (both primary and secondary) to reduce the

electromagnetic interferences, both radiated and conducted and passing more

easily the EMC regulations.

The below list can be used as guideline when designing a SMPS using VIPer16.

–

Signal ground routing should be routed separately from power ground and, in

general, from any pulsed high current loop;

–

Connect all the signal ground traces to the power ground, using a single "star

point", placed close to the IC GND pin;

–

With flyback topologies, when the auxiliary winding is used, it is suggested to

connect the VDD capacitor on the auxiliary return and then to the main GND using

a single track;

–

The compensation network should be connected as close as possible to the

COMP pin, maintaining the trace for the GND as short as possible;

–

A small bypass capacitor (a few hundreds pF up to 0.1 µF) to GND might be useful

to get a clean bias voltage for the signal part of the IC and protect the IC itself

during EFT/ESD tests. A low ESL ceramic capacitor should be used, placed as

close as possible to the VDD pin;

–

When using SO16 package it is recommended to connect the pin 4 to GND pin,

using a signal track, in order to improve the noise immunity. This is highly

recommended in case of high nosily environment;

–

An optional capacitor can be connected on the LIM pin in order to improve the IC

noise immunity. It is strongly recommended to don't exceed 470nF.

–

The IC thermal dissipation takes place through the drain pins. An adequate heat

sink copper area has to be designed under the drain pins to improve the thermal

dissipation;

–

It is not recommended to place large copper areas on the GND pins.

–

Minimize the area of the pulsed loops (primary, RCD and secondary loops), in

order to reduce its parasitic self- inductance and the radiated electromagnetic

field: this will greatly reduce the electromagnetic interferences produced by the

power supply during the switching.