DocID025703 Rev 2

21/31

VIPER38

Operation

31

During startup, when the output voltage is still low, if the feedback network is not properly

generating the switching off of the IC itself. Taking into account that the feedback network

also fixes the loop stability, two options can be considered for this network.

Equation 5

dual function: guaranteeing the loop compensation and fixing the overload delay time as

calculated in Equation 5.

Owing to the above considerations, the OLP delay time must be long enough to bypass the

initial output voltage transient and check the overload condition only when the output

voltage is in steady state. The output transient time depends on the value of the output

capacitor and on the load.

ensure enough OLP delay, an alternative compensation network can be used and it is

shown in Figure 24: FB pin configuration (option 2).

is usually used to compensate the high-frequency zero due to the ESR (equivalent series

resistor) of the output capacitance of the flyback converter.

The mathematical expressions of these poles and zero frequency are:

Equation 6

Equation 7

T

OLP

delay

–

C

FB

V

FBolp

V

FBlin

–

I

FB2

----------------------------------------

×

=

f

ZFB

1

2

π C

FB1

R

FB1

⋅⋅

⋅

-----------------------------------------------

=

f

PFB

R

FB DYN

()

R

FB1

+

2

π C

FB

R

FB DYN

⋅

()

⋅⋅

⋅

-------------------------------------------------------------------------------

=

()

)

DYN

(

FB

1

FB

1

FB

1

PFB

R

R

C

2

1

f

+

⋅

⋅

π

⋅

=