VIPER38LDTR datasheet(23/31 Pages) STMICROELECTRONICS

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VIPER38

Operation

7.11

Burst-mode operation at no load or very light load

When the load decreases, the feedback loop reacts by lowering the feedback pin voltage. If

it falls below the burst mode threshold, VFBbm, the power MOSFET is no longer allowed to

be switched on. After the MOSFET stops, the feedback pin voltage increases and when it

exceeds the level, VFBbm + VFBbmhys, the power MOSFET starts switching again. The burst

mode thresholds are provided in Table 8: Controller section and Figure 25: Burst mode

timing diagram, light load shows this behavior. The system alternates between a period of

time where the power MOSFET is switching to a period of time where the power MOSFET is

not switching. This mode of operation is the burst mode. The advantage of burst mode

operation is an average switching frequency much lower than the normal operation

frequency, up to several hundred hertz, minimizing all frequency-related losses. In order to

prevent audible noise, during burst mode the drain current peak is clamped to the level,

ID_BM, given in Table 8: Controller section.

Figure 25. Burst mode timing diagram, light load

7.12

Extra power timer (EPT)

The extra power timer feature allows the setting of a blanking time inside which an overload

current can be admitted. The timer is set through a capacitor (CEPT) connected to the EPT

pin. Its duration is in the range of a few seconds and is limited by thermal constraints.

The extra power timer (EPT) is started as soon as the drain current reaches the threshold

IDLIM_EPT (typ. 85% of IDlim) and its duration is defined by the time needed to charge the

capacitor CEPT up to the value VEPT(STOP) (4V, typ). The charging current is IEPT (-5 uA,

typ).

If the EPT starts, the IC sustains the overload and continues to operate normally if the drain

current falls below the threshold IDLIM_EPT (85% of IDlim) before the EPT voltage reaches the

value VEPT(STOP). The capacitor CEPT is discharged through the current IEPT (5 uA, typ) and

the next EPT is inhibited until the EPT voltage is higher than VEPT(RESTART) (0.6 V, typ). If

the EPT starts and the EPT voltage reaches the value VEPT(STOP), the IC stops and it is

automatically restarted. The CVDD capacitor is then discharged down to the value

VDD(RESTART) (4.5 V, typ) and is recharged, through the HV current source, up to the value

VDDon (14 V, typ). Also in this case the capacitor CEPT is discharged through the IEPT

current. See Figure 26: EPT timing diagram and Table 7: Supply section. The EPT pin has

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