TLF6407

June 1989

54LS194ADM74LS194A 4-Bit

Bidirectional Universal Shift Register

General Description

This bidirectional shift register is designed to incorporate

virtually all of the features a system designer may want in a

shift register they feature parallel inputs parallel outputs

right-shift and left-shift serial inputs operating-mode-control

inputs and a direct overriding clear line The register has

four distinct modes of operation namely

Parallel (broadside) load

Inhibit clock (do nothing)

Synchronous parallel loading is accomplished by applying

the four bits of data and taking both mode control inputs S0

and S1 high The data is loaded into the associated flip-

flops and appear at the outputs after the positive transition

of the clock input During loading serial data flow is inhibit-

ed

Shift right is accomplished synchronously with the rising

edge of the clock pulse when S0 is high and S1 is low

Serial data for this mode is entered at the shift-right data

input When S0 is low and S1 is high data shifts left syn-

chronously and new data is entered at the shift-left serial

input

Clocking of the flip-flop is inhibited when both mode control

inputs are low

Features

Y

Parallel inputs and outputs

Y

Four operating modes

Synchronous parallel load

Right shift

Left shift

Do nothing

Y

Positive edge-triggered clocking

Y

Direct overriding clear

Connection Diagram

Dual-In-Line Package

TLF6407 – 1

Order Number 54LS194ADMQB 54LS194AFMQB

54LS194ALMQB DM74LS194AM or DM74LS194AN

See NS Package Number E20A J16A M16A N16E or W16A

C1995 National Semiconductor Corporation

RRD-B30M105Printed in U S A