LAN91C94 datasheet(5/120 Pages) SMSC

5 / 120 page

GENERAL DESCRIPTION

The LAN91C94 is a VLSI Ethernet Controller

that combines ISA and PCMCIA interfaces in

one chip. LAN91C94 integrates all the MAC and

physical layer functions, as well as the packet

RAM, needed to implement a high performance

10BASE-T (twisted pair) node. For 10BASE5

(thick

coax),

10BASE2

(thin

coax),

and

10BASE-F

(fiber)

implementations,

the

LAN91C94 interfaces to external transceivers

via its AUI port.

Only one additional IC is

required on most applications. The LAN91C94

occupies 16 I/0 locations and no memory space

except for PCMCIA attribute memory space. The

same I/O space is used for both ISA and

PCMCIA

operations.

The

LAN91C94

can

directly interface the ISA and PCMCIA buses

and deliver no wait state operation. Its shared

memory is sequentially accessed

with 40ns

access times to any of its registers, including its

packet memory. No DMA services are used by

the LAN91C94, virtually decoupling network

traffic from local or system bus utilization. For

packet memory management, the LAN91C94

integrates

unique

hardware

Memory

Management

Unit

(MMU)

with

enhanced

performance and decreased software overhead

when compared to ring buffer and linked list

architectures.

The LAN91C94 is portable to

different CPU and bus platforms due to its

flexible bus interface, flat memory structure (no

pointers), and its loosely coupled buffered

architecture (not sensitive to latency).

OVERVIEW

A unique architecture allows the LAN91C94 to

combine

high

performance,

flexibility,

high

integration and simple software interface.

The LAN91C94 incorporates the LAN91C92

functionality for ISA environments, as well as a

PCMCIA interface and attribute registers. Mode

selection between ISA and PCMCIA is static and

is done only once at the end of a reset. The

LAN91C94 consists of the same logical

I/O

However, some of the signals used to access

the PCMCIA differ from the ISA mode.

The

MMU

(Memory

Management

Unit)

architecture used by the LAN91C94 combines

the simplicity and low overhead of fixed areas

with the flexibility of linked lists providing

improved performance over other methods.

Packet

reception

and

transmission

are

determined by memory availability.

All other

resources are always available if memory is

available.

complement

this

flexible

architecture, all ISA bus interface functions are

incorporated in the LAN91C94, as well as a

4608 byte packet RAM and serial EEPROM-

based setup.

The user can select or modify

configuration choices.

The LAN91C94 integrates most of the 802.3

functionality,

incorporating

the

MAC

layer

protocol,

the

physical

layer

encoding

and

decoding functions with the ability to handle the

AUI interface.

For twisted pair networks,

LAN91C94

integrates

the

twisted

pair

transceiver as well as the link integrity test

functions.

The LAN91C94 is a true 10BASE-T single chip

able to interface a system or a local bus.

Directly-driven LEDs for installation and run-

time diagnostics are provided, as well as 802.3

statistics

gathering

facilitate

network

management.

LAN91C94 数据表(PDF) 5 Page - SMSC Corporation

LAN91C94 数据表(HTML) 5 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载