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Rev.1.1

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Figure 12. Dual I/O Fast Read Sequence Diagram (M7-0 = 0XH or not AXH)

Command

0 1 2 3 4 5 6 7

BBH

CS#

SCLK

SI(IO0)

SO(IO1)

8 9 10 11 12 13 14 15

6 4 2 0 6 4 2 0

16 17 18 19 20 21 22 23

6 4 2 0 6 4 2 0

7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1

A23-16

A15-8

A7-0

M7-0

CS#

23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

SI(IO0)

SO(IO1)

6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0

7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1

SCLK

6

7

Byte1

Byte2

Byte3

Byte4

Figure 13. Dual I/O Fast Read Sequence Diagram (M7-0 = AXH)

0 1 2 3 4 5 6 7

CS#

SCLK

8 9 10 11 12 13 14 15

6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0

7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1

A23-16

A15-8

A7-0

M7-0

CS#

23 24 25 26 27 28 29 30 31

SI(IO0)

SO(IO1)

6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0

7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1

SCLK

6

7

Byte1

Byte2

Byte3

Byte4

15 16 17 18 19 20 21 22

7.12. Quad I/O Fast Read (EBH)

The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to

input the 3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit per clock

by IO0, IO1, IO3, IO4, each bit being latched in during the rising edge of SCLK, then the memory contents

are shifted out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The command sequence is shown in followed

Figure14. The first byte addressed can be at any location. The address is automatically incremented to the next

higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must