CS35L32 datasheet(13/51 Pages) CIRRUS

13 / 51 page

DS963F5

CS35L32

3 Characteristics and Specifications

Table 3-12. Switching Specifications: ADSP in I2S Mode

Test conditions, except where noted otherwise: VA = 1.8 V, VP = 3.6 V, VBST = 5.0 V, TA = +25°C, Inputs: Logic 0 = GNDA = GNDP = 0 V, Logic 1 =

VA; CLOAD = 30 pF. Section 9 describes some parameters in detail; input timings are measured at VIL and VIH thresholds; output timings are measured

at VOL and VOH thresholds (see Table 3-8).

Parameters

Symbol 1

1.ADSP timing in I2S Mode

Min

Max

Units

Slave Mode

Input sample rate (LRCK) 2

2.Clock rates should be stable when the CS35L32 is powered up.

—

kHz

LRCK duty cycle

—

SCLK frequency

1/tPs

—

64•Fs

SCLK duty cycle

—

LRCK setup time before SCLK rising edge

tSS(LK–SK)

—

LRCK hold time after SCLK rising edge

tHS(SK–LK)

—

SDOUT time from SCLK to data valid start 3

3.Minimum data valid window, as shown in signal diagram, is (SCLKperiod – 300 + 155) ns. For SCLK = 64*Fs =64*48 = 3072 kHz, this is 180 ns.

tDataValidStrt

—

300

SDOUT time from SCLK to data valid end 3

tDataValidEnd

155

—

Master Mode

OUTPUT sample rate (LRCK) 4

4.In Master Mode, the output sample rate follows MCLK rate divided down per Table 4-14 and Section 7.7. Any deviation in internal MCLK from the

nominal supported rates is directly imparted to the output sample rate by the same factor (e.g., +100-ppm offset in the frequency of MCLK becomes

a +100-ppm offset in LRCK).

—

[4]

kHz

LRCK duty cycle

—

SCLK frequency

1/tPM

—

64•Fs

SCLK duty cycle

RATIO = 0

RATIO = 1 [5]

5.If RATIO = 1, the MCLK(INT)-to-LRCK ratio is 125. The device periodically extends SCLK high time to compensate for a fractional MCLK/SCLK ratio

—

LRCK setup time before SCLK rising edge

tSM(LK–SK)

—

LRCK hold time after SCLK rising edge

tHM(SK–LK)

—

SDOUT time from SCLK to data valid start 3

tDataValidStrt

—

300

SDOUT time from SCLK to data valid end 3

tDataValidEnd

155

—

LRCK

SCLK

SDOUT

TP

Note:

 = “S” or “M”

tS(LK-SK)

tH(SK-LK)

tDataValidStrt

tDataValidEnd

DataValidWind

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