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AD9410/PCB 数据表(PDF) 2 Page - Analog Devices |
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AD9410/PCB 数据表(HTML) 2 Page - Analog Devices |
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2 / 20 page ![]() REV. 0 –2– AD9410–SPECIFICATIONS DC SPECIFICATIONS Test Parameter Temp Level Min Typ Max Unit RESOLUTION 10 Bits DC ACCURACY No Missing Codes 1 Full IV Guaranteed Differential Nonlinearity 25 °C I –1.0 ±0.5 +1.25 LSB Full VI –1.0 +1.5 LSB Integral Nonlinearity 25 °C I –2.5 ±1.65 +2.5 LSB Full VI –3.0 +3.0 LSB Gain Error 25 °C I –6.0 0 +6.0 % FS Gain Tempco Full V 130 ppm/ °C ANALOG INPUT Input Voltage Range (With Respect to AIN) Full V ±768 mV p-p Common-Mode Voltage Full V 3.0 V Input Offset Voltage 25 °C I –15 +3 +15 mV Full VI –20 +20 mV Reference Voltage Full VI 2.4 2.5 2.6 V Reference Tempco Full V 50 ppm/ °C Input Resistance Full VI 610 875 1250 Ω Input Capacitance 25 °CV 3 pF Analog Bandwidth, Full Power 25 °C V 500 MHz POWER SUPPLY Power Dissipation AC 2 25 °C V 2.1 W Power Dissipation DC3 Full VI 2.0 2.4 W IVCC 3 Full VI 128 145 mA IVD 3 Full VI 401 480 mA Power Supply Rejection Ratio PSRR 25 °C I –7.5 +0.5 +7.5 mV/V NOTES 1Package heat slug should be attached when operating at greater than 70 °C ambient temperature. 2Encode = 210 MSPS, A IN = –0.5 dBFS 10 MHz sine wave, IVDD = 31 mA typical at CLOAD = 5 pF. 3Encode = 210 MSPS, A IN = dc, outputs not switching. Specifications subject to change without notice. SWITCHING SPECIFICATIONS Test Parameter Temp Level Min Typ Max Unit SWITCHING PERFORMANCE Maximum Conversion Rate Full VI 210 MSPS Minimum Conversion Rate Full IV 100 MSPS Encode Pulsewidth High (tEH)25 °C IV 1.2 2.4 ns Encode Pulsewidth Low (tEL)25 °C IV 1.2 2.4 ns Aperture Delay (tA)25 °C V 1.0 ns Aperture Uncertainty (Jitter) 25 °C V 0.65 ps rms Output Valid Time (tV) Full VI 3.0 ns Output Propagation Delay (tPD) Full VI 7.4 ns Output Rise Time (tR)25 °C V 1.8 ns Output Fall Time (tF)25 °C V 1.4 ns CLKOUT Propagation Delay 1 (t CPD) Full VI 2.6 4.8 6.4 ns Data to DCO Skew (tPD–tCPD) Full IV 0 1 2 ns DS Setup Time (tSDS) Full IV 0.5 ns DS Hold Time (tHDS) Full IV 0 ns Interleaved Mode (A, B Latency) Full VI A = 6, B = 6 Cycles Parallel Mode (A, B Latency) Full VI A = 7, B = 6 Cycles NOTES 1C LOAD = 5 pF. Specifications subject to change without notice. (VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = –0.5 dBFS; Clock input = 210 MSPS; TA = 25 C; unless otherwise noted.) (VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = –0.5 dBFS; Clock input = 210 MSPS; TA = 25 C; unless otherwise noted.) |
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