WM8805 datasheet(21/66 Pages) CIRRUS

21 / 66 page

Production Data

WM8805

PD, Rev 4.5, March 2009

MASTER CLOCK AND PHASE LOCKED LOOP

SOFTWARE MODE INTERNAL CLOCKING

The WM8805 is equipped with a comprehensive clocking scheme that provides maximum flexibility

and function and many configurable routing possibilities for the user in software mode. An overview

of the software mode clocking scheme is shown in Figure 16.

Figure 16 Software Mode Clocking Scheme Overview

The clocking scheme can be divided into four sections. These are detailed as follows:

OSCILLATOR

The primary function of the oscillator is to generate the oscillator clock (OSCCLK) for the PLL input.

Whenever the PLL or the S/PDIF receiver is enabled, the oscillator must be used to generate the

OSCCLK signal for the PLL.

The secondary function of the oscillator is to generate the OSCCLK so that it can be selected

internally as the clock source for:

•

The MCLK output pin, when the pin is configured as an output.

•

The CLKOUT output pin, when enabled.

The oscillator has one control bit as shown in Table 19. The oscillator must be powered up to

generate the OSCCLK signal.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R30

PWRDN

1Eh

OSCPD

Oscillator Power Down Control

0 = Power up

1 = Power down

Table 19 Oscillator Control

WM8805 数据表(PDF) 21 Page - Cirrus Logic

WM8805 数据表(HTML) 21 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

数据表下载