AMBE-2000™ Vocoder Chip

User’s Manual Version 3.0

page 13

Confidential Proprietary, Subject to Change

3.3

Clock and Reset Timing

To reset the AMBE-2000 chip, the reset signal must be held low for a minimum of six clock cycles. The recovery time from

reset is approximately 95 msec. In other words, 95 msec after the rising edge of the reset signal the AMBE-2000 starts

processing PCM samples. The first packet will be ready after 252 PCM samples are read.

Figure 3-A X2/CLKIN and CLKOUT Timing Diagram

Table 3-A X2/CLKIN and CLKOUT Timing Parameters

Reference

Parameter

Min

Max

Units

Cycle time,

X2/CLKIN

Integer PLL multiplier N (N=4)

20

400

ns

Fall time, X2/CLKIN

4

ns

Rise time, X2/CLKIN

4

ns

Pulse duration, X2/CLKIN low

6

ns

Pulse duration, X2/CLKIN high

6

ns

Transitory phase, PLL lock-up time

50

Cycle time, CLKOUT (typical is

15

ns

Delay time, X2/CLKIN high/low to CLKOUT high/low

4

16

ns

Pulse duration, CLKOUT low

H-4

H

ns

Pulse duration, CLKOUT high

H-4

H

ns

•

CLKOUT is shown for reference only. It is not to be connected in the circuit.

•

H = 7.629 ns

Unstable

tp

t

t

t

t

t

t

t

t

t

t

t

X2/CLKIN

CLKOUT