W55P241

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Chip

Select

Clock

Data

Output

(MSB first)

Sample

Data

MSB

LSB

Bit N

Bit M

..

…

..

…

..

…

Changing data

Latching data

Idle

“0”

Idle

“0”

Figure 3 SPI mode 0 (MSB first)

5.1.3

Command Protocol

One SPI transfer consists of one command byte and one data byte. Because the 1

“transmit data” are regarded as command byte after the falling edge of /CS, it is not possible that /CS

remains

“0’ during two successive SPI transfers. The last 8 bits of “transmit data” in one SPI transfer

are regarded as data bytes. For both command byte and data byte to be identified by the W55P241,

MSB (Most Significant Bit) is transferred first. When the microcontroller writes data to W55P241, DO

remains in high impedance state during the whole SPI transfer. When the microcontroller reads data

from the W55P241, DO remains in high impedance state until the data byte is generated.