2

Integrated

Circuit

Systems, Inc.

ICS950902

0475G—03/23/04

General Description

The ICS950902 is a single chip clock solution for desktop designs using the VIA P4X/P4M/KT/KN266/333 style chipsets with

PC133 or DDR memory.

The ICS950902 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part

incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a

serially programmable I

divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each

individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.

Block Diagram

DDRC (5:0)/SDRAM (10,8,6,4,2,0)

DDRC (5:0)/SDRAM (11,9,7,5,3,1)

FBOUT

Power Groups

VDD

GND

55

2

Xtal, Ref

5

9

AGP [0:2], CPU digital, CPU PLL

16

13

PCI [0:5], PCI_F outputs

22

19

48MHz, Fix Digital, Fix Analog

23

24

Master clock, CPU Analog

34, 40

33, 39

DDR/SDR outputs

50

47

2.5V CPUT/C_CS output

51

54

3.3V CPUT/C & CPUOD_T/C

Pin Number

Description