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RT8092BCGWSC 数据表(PDF) 16 Page - Richtek Technology Corporation

部件名 RT8092BCGWSC
功能描述  High Efficiency Step-Down Converter
PDF  27 Pages
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制造商  RICHTEK [Richtek Technology Corporation]
网页  http://www.richtek.com
标志 RICHTEK - Richtek Technology Corporation

RT8092BCGWSC 数据表(HTML) 16 Page - Richtek Technology Corporation

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RT8092
16
DS8092-03
January 2017
www.richtek.com
©
Copyright
2017 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
of bulk capacitance is also a key for COUT selection to
ensure that the control loop is stable. Loop stability can
be checked by viewing the load transient response. The
output voltage ripple, VOUT, is determined by :

  


OUT
L
OSC
OUT
1
V
I
ESR +
8f
C
where fOSC is the switching frequency and IL is the inductor
ripple current.
The output voltage ripple will be the highest at the
maximum input voltage since IL increases with input
voltage. Multiple capacitors placed in parallel may be
needed to meet the ESR and RMS current handling
requirement. Ceramic capacitors have excellent low ESR
characteristics, but can have a high voltage coefficient
and audible piezoelectric effects. The high Q of ceramic
capacitors with trace inductance can also lead to significant
ringing. Nevertheless, high value, low cost ceramic
capacitors are now becoming available in smaller case
sizes. Their high ripple current, high voltage rating and
low ESR make them ideal for switching regulator
applications.
VSEL Function Selection
Figure 5 shows the detailed logic of VSEL function. There
are several parameters can be set its initial condition,
such as output voltage, operation mode (Auto PSM/PWM
or Forced-PWM) and output voltage bank. Users can set
separately into VSEL high state and VSEL low state to
design the required performance.
Figure 5. VSEL Logic
0x11.ENSEL0
0x11.VoutSEL0[6:0]
0x10.VoutSEL1[6:0]
VoutSEL[6:0]
0x10.ENSEL1
ENSEL
DVS
VREF Control
Enable Control
Buck
Converter
0x14.PWM0
0x14.PWM1
EN
VSEL
PWM
FPWM
Auto
Mode Control
Chosen by VSEL
0x1D.VOUT_BANK0[1:0]
0x1C.VOUT_BANK1[1:0]
Feedback
Network
Feedback
Control
VOUT_BANK
MUX2
0
1
MUX2
0
1
MUX2
0
1
MUX2
0
1
MUX2
0
1



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