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ADCS9888 数据表(PDF) 7 Page - National Semiconductor (TI) |
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ADCS9888 数据表(HTML) 7 Page - National Semiconductor (TI) |
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7 / 34 page ![]() Pin Descriptions (Continued) Pin Label Type Description Power Supply 1, 6, 7, 10, 14, 18, 21, 25, 26, 34, 37 V D Power Supply Main power supply for analog and digital circuitry inside the IC. The data outputs and PLL are powered from separate buses for additional noise isolation. 56, 69, 79, 89, 98, 102, 112, 122 V DD Power Supply Power supply for digital data outputs. This voltage can be operated at voltages below the Main Power Supply, down to 2.5V, to provide convenient interfaces to lower voltage circuitry. 47, 48, 52 PV D Power Supply Phase Locked Loop Power Supply. This input should be well filtered, isolated, and decoupled, to provide a very stable, low noise, voltage source for the PLL and VCO circuitry in the ADCS9888. 3, 4, 11, 15, 19, 22, 27, 28, 35, 36, 40, 41, 46, 49, 51, 55, 65-68, 78, 88, 99-101, 111, 121, 128 GND Ground Ground Return. Ground return for all circuitry on the chip. For best performance, the printed circuit board should be designed using a single solid ground plane. Other ICs should be placed to minimize the effects of noisy digital ground returns interfering with the ADCS9888 operation. 39, 39 NC NC To ensure compliance with designs using the AD9888, these pins are not connected to the IC die. They may be physically connected to either V D or PV D with no effect on operation, performance, or reliability. www.national.com 7 |
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