PC87372 datasheet(2/144 Pages) NSC

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Revision 1.2

Features

Bus Interface

LPC Bus Interface

— Based on Intel’s LPC Interface Speciﬁcation Revi-

sion 1.0, September 29, 1997

— Synchronous cycles using up to 33 MHz bus clock

— 8-bit I/O read and write cycles

— Up to four 8-bit DMA channels

— Serial IRQ (SERIRQ)

— Reset input (PCI_RESET)

— Optional power-down support (LPCPD)

Configuration Control

— PnP Conﬁguration Register structure

— Compliant with PC01 Speciﬁcation Revision 1.0,

1999-2000

— Base Address strap (BADDR) to setup the address

of the Index-Data register pair (defaults to 2Eh/2Fh)

— Flexible resource allocation for all logical devices:

❏

Relocatable base address

❏

15 IRQ routing options to serial IRQ

❏

Up to four optional 8-bit DMA channels

— Conﬁgurable feature sets:

❏

Software selectable

❏

VSB3-powered pin multiplexing

Legacy Modules

Serial Port

— Software compatible with the NS16550A and the

NS16450

— Supports shadow register for write-only bit monitoring

— Data rates up to 1.5 Mbaud

IEEE 1284-compliant Parallel Port

— ECP, with Level 2 (14 mA sink and source output

buffers)

— Software or hardware control

— Enhanced Parallel Port (EPP) compatible with EPP

1.7 and EPP 1.9

— Supports EPP as mode 4 of the Extended Control

— Selection of internal pull-up or pull-down resistor for

Paper End (PE) pin

— Supports a demand DMA mode mechanism and a

DMA fairness mechanism for improved bus utilization

— Protection circuit that prevents damage to the

parallel port when a printer connected to it is pow-

ered up or is operated at high voltages (in both

cases, even if the PC87372 is in power-down state)

Floppy Disk Controller (FDC)

— Software compatible with the PC8477 (the PC8477

contains a superset of the FDC functions in the

µDP8473, NEC µPD765A/B and N82077 devices)

— Error-free handling of data overrun and underrun

— Programmable write protect

— Supports FM and MFM modes

— Supports Enhanced mode command for three-mode

Floppy Disk Drive (FDD)

— Perpendicular

recording

drive

support

for

2.88 MBytes

— Burst (16-byte FIFO) and Non-Burst modes

— Full support for IBM Tape Drive Register (TDR) im-

plementation of AT and PS/2 drive types

— High-performance digital separator

— Supports fast tape drives (2 Mbps) and standard

tape drives (1 Mbps, 500 Kbps and 250 Kbps)

Keyboard and Mouse Controller (KBC)

— 8-bit

microcontroller,

software

compatible

with

8042AH and PC87911

— Standard interface (60h, 64h, IRQ1 and IRQ12)

— Supports two external swapable PS/2 interfaces for

keyboard and mouse

— Programmable, dedicated quasi-bidirectional I/O

lines (GA20/P21, KBRST/P20)

General-Purpose Modules

General-Purpose I/O (GPIO) Ports

— 13 GPIO ports powered by VSB3

— Each pin individually conﬁgured as input or output

— Programmable features for each output pin:

❏

Drive

type

(open-drain,

push-pull

TRI-STATE)

❏

TRI-STATE on detection of falling VDD3 for

VSB3-powered pins driving VDD-supplied devices

— Programmable option for internal pull-up resistor on

each input pin

— Lock option for the conﬁguration and data of each

output pin

— 12 GPIO ports generate IRQ/SIOPME for wake-up

events; each GPIO has separate:

❏

Enable control of event status routing to IRQ

❏

Enable control of event status routing to SIOPME

❏

Polarity and edge/level selection

❏

Programmable debouncing

Glue Functions

— Software selectable alternative functionality, through

pin multiplexing

— Generates the power-related signals:

❏

Main Power good

❏

Power distribution control (for switching between

Main and Standby regulators)

❏

Resume reset (Master Reset) according to the

5V standby supply status

❏

Main power supply turn on (PS_ON)

❏

Rambus SCK clock gating

— Voltage translation between 3.3V levels (DDC) and

5V levels (VGA) for the SMBus serial clock and data

signals

— Isolation circuitry for the SMBus serial clock and

data signals

— Buffers PCI_RESET to generate three reset output

signals

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