LM3520 datasheet(6/14 Pages) NSC

6 / 14 page

Electrical Characteristics (Notes 6, 7) Limits in standard typeface are for T

J = +25˚C. Limits in boldface

type apply over the full operating junction temperature range (−40˚C

≤ =T

≤ +125˚C). Unless otherwise noted: specifications

apply to the LM3520. V

IN = 3.6V, V(En) > 1.0V, CIN = 10 µF (Note 8). (Continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

OVP

Output Over-Voltage Protection

ON Threshold

22.2

23.2

24.2

(Main & Sub Displays)

OFF Threshold

21.5

22.5

23.5

UVP

Input Under-Voltage Protection

ON Threshold

2.3

2.4

2.5

OFF Threshold

2.35

2.45

2.55

Vout_main_leak

OUT Leakage Current

OUT =VIN, MAIN_EN =

SUB_EN = 0V

0.1

Vout_main_bias

OUT Bias Current at No Load

OUT = 20V, SUB_EN = 0

150

µA

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of

the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the

Electrical Characteristics tables.

Note 2: Enable signal must not be higher than Input voltage.

Note 3: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be

derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125

oC), the maximum power

dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the

following equation: TA-MAX =TJ-MAX-OP –(θJA xPD-MAX).

Note 4: The Human body model is a 100 pF capacitor discharged through a 1.5 k

Ω resistor into each pin. The machine model is a 200 pF capacitor discharged

directly into each pin. MIL-STD-883 3015.7

Note 5: Junction-to-ambient thermal resistance (

θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the JEDEC

standard JESD51-7. The test board is a 4-layer FR-4 board measuring 101.6mm x 76.2mm x 1.6mm. Thickness of the copper layers are 2oz/1oz/1oz/2oz. The

middle layer of the board is 60mm x 60mm. Ambient temperature in simulation is 22˚C, still air.

Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care

must be paid to thermal dissipation issues in board design.

Note 6: All voltage is with respect toGND.

Note 7: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.

Note 8: CIN and COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

Note 9: Feedback current flows out of the Sub_ FB pin.

Note 10: Current flows into the pin.

LM3520 数据表(PDF) 6 Page - National Semiconductor (TI)

LM3520 数据表(HTML) 6 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14

数据表下载