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PALCE29MA16 数据表(PDF) 13 Page - Advanced Micro Devices |
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PALCE29MA16 数据表(HTML) 13 Page - Advanced Micro Devices |
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13 / 25 page ![]() AMD 2-361 PALCE29MA16H-25 (Com’l) CAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions Typ Unit CIN Input Capacitance VIN = 0 V VCC = 5.0 V, TA = 25 °C, 5 pF COUT Output Capacitance VOUT = 0 V f = 1 MHz 8 pF Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS Registered Operation Parameter Symbol Parameter Description Min Max Unit Combinatorial Output tPD Input or I/O Pin to Combinatorial Output 25 ns Output Register – Pin Clock tSOR Input or I/O Pin to Output Register Setup 15 ns tCOR Output Register Clock to Output 15 ns tHOR Data Hold Time for Output Register 0 ns Output Register – Product Term Clock tSORP I/O Pin or Input to Output Register Setup 4 ns tCORP Output Register Clock to Output 29 ns tHORP Data Hold Time for Output Register 10 ns Input Register – Pin Clock tSIR I/O Pin to Input Register Setup 2 ns tCIR Register Feedback Clock to Combinatorial Output 28 ns tHIR Data Hold time for Input Register 6 ns Clock and Frequency tCIS Register Feedback (Pin Driven Clock) to Output 20 ns Register/Latch (Pin Driven) Setup tCISPP Register Feedback (PT Driven Clock) to Output 25 ns Register/Latch (PT Driven) Setup fMAX Maximum Frequency (Pin Driven) 1/(tSOR + tCOR) 33.3 MHz fMAXI Maximum Internal Frequency (Pin Driven) 1/tCIS 50 MHz fMAXP Maximum Frequency (PT Driven) 1/(tSORP + tCORP) 30 MHz fMAXIPP Maximum Internal Frequency (PT Driven) 1/tCISPP 40 MHz tCWH Pin Clock Width HIGH 8 ns tCWL Pin Clock Width LOW 8 ns tCWHP PT Clock Width HIGH 12 ns tCWLP PT Clock Width LOW 12 ns |
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